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2020-06-23block/nvme: don't access CQE after moving cq.headStefan Hajnoczi1-1/+4
2020-06-23block/nvme: drop tautologous assertionStefan Hajnoczi1-1/+0
2020-06-23block/nvme: poll queues without q->lockStefan Hajnoczi1-0/+12
2020-06-23check-block: enable iotests with SafeStackDaniele Buono1-1/+11
2020-06-23configure: add flags to support SafeStackDaniele Buono1-0/+73
2020-06-23coroutine: add check for SafeStack in sigaltstackDaniele Buono1-0/+4
2020-06-23coroutine: support SafeStack in ucontext backendDaniele Buono2-0/+33
2020-06-23minikconf: explicitly set encoding to UTF-8Stefan Hajnoczi1-3/+3
2020-06-19qht: Fix threshold rate calculationRichard Henderson1-1/+2
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2-0/+5
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2-8/+37
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng3-15/+17
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2-0/+8
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng1-1/+23
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng1-1/+3
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2-2/+60
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng2-11/+22
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng2-11/+9
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng1-0/+11
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng1-6/+1
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-15/+14
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-12/+12
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis1-5/+9
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis2-2/+36
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis2-2/+15
2020-06-19hw/intc: Initial commit of lowRISC Ibex PLICAlistair Francis4-0/+327
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis5-0/+609
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis1-1/+2
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis3-26/+24
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis4-41/+63
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis1-2/+7
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis1-1/+1
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng1-4/+4
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng1-21/+10
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng1-14/+6
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng1-13/+5
2020-06-19sifive_e: Support the revB machineAlistair Francis2-4/+31
2020-06-19riscv: Add helper to make NaN-boxing for FP registerIan Jiang1-2/+15
2020-06-19hw/audio/gus: Fix registers 32-bit accessAllan Peramaki2-2/+2
2020-06-18net: Drop the NetLegacy structure, always use Netdev insteadThomas Huth2-110/+13
2020-06-18net: Drop the legacy "name" parameter from the -net optionThomas Huth3-18/+10
2020-06-18hw/net/e1000e: Do not abort() on invalid PSRCTL register valuePhilippe Mathieu-Daudé1-3/+7
2020-06-18colo-compare: Fix memory leak in packet_enqueue()Derek Su2-8/+16
2020-06-18net/colo-compare.c: Correct ordering in complete and finalizeLukas Straub1-22/+23
2020-06-18net/colo-compare.c: Check that colo-compare is activeLukas Straub1-6/+29
2020-06-18net/colo-compare.c: Only hexdump packets if tracing is enabledLukas Straub1-4/+6
2020-06-18net/colo-compare.c: Fix deadlock in compare_chr_sendLukas Straub3-45/+156