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path: root/rust/qemu-api-macros/src/utils.rs (unfollow)
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2025-03-04hw/intc/aplic: refine kvm_msicfgaddrYong-Xuan Wang1-11/+13
2025-03-04hw/intc/aplic: refine the APLIC realizeYong-Xuan Wang1-23/+26
2025-03-04hw/intc/imsic: refine the IMSIC realizeYong-Xuan Wang1-21/+26
2025-03-04binfmt: Add --ignore-family optionAndrea Bolognani1-3/+16
2025-03-04binfmt: Normalize host CPU architectureAndrea Bolognani1-19/+25
2025-03-04binfmt: Shuffle things aroundAndrea Bolognani1-7/+10
2025-03-04target/riscv/kvm: Add some exts supportQuan Zhou1-0/+5
2025-03-04docs/specs/riscv-iommu.rst: add HPM support infoDaniel Henrique Barboza1-0/+2
2025-03-04hw/riscv: add IOMMU HPM trace eventsDaniel Henrique Barboza2-0/+15
2025-03-04hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM capTomasz Jeznach1-0/+21
2025-03-04hw/riscv/riscv-iommu: add hpm events mmio writeTomasz Jeznach4-1/+93
2025-03-04hw/riscv/riscv-iommu: add IOHPMCYCLES mmio writeTomasz Jeznach3-1/+21
2025-03-04hw/riscv/riscv-iommu: add IOCOUNTINH mmio writesTomasz Jeznach3-0/+99
2025-03-04hw/riscv/riscv-iommu: instantiate hpm_timerTomasz Jeznach4-0/+42
2025-03-04hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()Tomasz Jeznach4-15/+162
2025-03-04hw/riscv/riscv-iommu: add riscv-iommu-hpm fileTomasz Jeznach5-2/+110
2025-03-04hw/riscv/riscv-iommu-bits.h: HPM bitsTomasz Jeznach1-0/+47
2025-03-04hw/riscv/riscv-iommu.h: add missing headersDaniel Henrique Barboza1-0/+2
2025-03-04target/riscv/kvm: add extensions after 6.14-rc3 updateDaniel Henrique Barboza1-0/+3
2025-03-04target/riscv/cpu.c: create flag for ziccrseDaniel Henrique Barboza3-1/+7
2025-03-04linux-headers: Update to Linux v6.14-rc3Daniel Henrique Barboza13-35/+146
2025-03-04target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entryRob Bradford1-1/+1
2025-03-04target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.Rajnesh Kanwal3-2/+185
2025-03-04target/riscv: remove warnings about Smdbltrp/Smrnmi being disabledClément Léger1-5/+3
2025-03-04target/riscv: Mask out upper sscofpmf bits during validationAtish Patra1-1/+1
2025-03-04target/riscv: Fix the hpmevent maskAtish Patra1-3/+2
2025-03-04disas/riscv: Add missing Sdtrig CSRsRob Bradford1-1/+3
2025-03-04disas/riscv: Fix minor whitespace issuesRob Bradford1-6/+6
2025-03-04target/riscv: log guest errors when reserved bits are set in PTEsjulia1-1/+26
2025-03-04target/riscv: machine: Add Control Transfer Record state descriptionRajnesh Kanwal1-0/+25
2025-03-04target/riscv: Add CTR sctrclr instruction.Rajnesh Kanwal6-0/+50
2025-03-04target/riscv: Add support to record CTR entries.Rajnesh Kanwal8-0/+430
2025-03-04target/riscv: Add support for Control Transfer Records extension CSRs.Rajnesh Kanwal3-0/+151
2025-03-04target/riscv: Add Control Transfer Records CSR definitions.Rajnesh Kanwal1-0/+145
2025-03-04target/riscv: Remove obsolete sfence.vm instructionRajnesh Kanwal2-6/+0
2025-03-04MAINTAINERS: Remove Bin Meng from RISC-V maintainersAlistair Francis1-4/+1
2025-03-04hw/riscv/virt: Add serial alias in DTBVasilis Liaskovitis1-0/+3
2025-03-04goldfish_rtc: Fix tick_offset migrationRodrigo Dias Correa1-30/+13
2025-03-04hw/riscv/riscv-iommu-bits: Remove duplicate definitionsJason Chien1-16/+6
2025-03-04hw/riscv/riscv-iommu: Remove redundant struct membersJason Chien1-5/+0
2025-03-04target/riscv: add RVA23S64 profileDaniel Henrique Barboza2-0/+40
2025-03-04target/riscv: add RVA23U64 profileDaniel Henrique Barboza2-0/+34
2025-03-04target/riscv: change priv_ver check in validate_profile()Daniel Henrique Barboza1-1/+1
2025-03-04target/riscv: add profile u_parent and s_parentDaniel Henrique Barboza3-12/+32
2025-03-04target/riscv: use RVB in RVA22U64Daniel Henrique Barboza2-1/+1
2025-03-04target/riscv: add ssu64xlDaniel Henrique Barboza2-0/+1
2025-03-04hw/intc/riscv_aplic: Remove redundant "hart_idx" maskingHuang Borong1-1/+0
2025-03-04target/riscv: throw debug exception before page faultDaniel Henrique Barboza1-0/+18
2025-03-04target/riscv/debug.c: use wp size = 4 for 32-bit CPUsDaniel Henrique Barboza1-2/+4
2025-03-04target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_setMax Chou1-2/+3