summary refs log tree commit diff stats
path: root/rust/qemu-api-macros/src/utils.rs (unfollow)
Commit message (Expand)AuthorFilesLines
2025-01-28rust: pl011: pull device-specific code out of MemoryRegionOps callbacksPaolo Bonzini2-26/+15
2025-01-28rust: pl011: remove duplicate definitionsPaolo Bonzini2-49/+29
2025-01-28rust: pl011: wrap registers with BqlRefCellPaolo Bonzini2-22/+32
2025-01-27rust: pl011: extract PL011RegistersPaolo Bonzini2-127/+166
2025-01-27rust: pl011: pull interrupt updates out of read/write opsPaolo Bonzini1-36/+48
2025-01-27rust: pl011: extract CharBackend receive logic into a separate functionPaolo Bonzini1-6/+9
2025-01-27rust: pl011: extract conversion to RegisterOffsetPaolo Bonzini2-60/+79
2025-01-23rust: pl011: hide unnecessarily "pub" items from outside pl011::devicePaolo Bonzini3-7/+10
2025-01-23rust: pl011: remove unnecessary "extern crate"Paolo Bonzini1-4/+0
2025-01-23rust: prefer NonNull::new to assertionsPaolo Bonzini5-47/+35
2025-01-23rust: vmstate: make order of parameters consistent in vmstate_clockPaolo Bonzini2-2/+2
2025-01-23rust: vmstate: remove translation of C vmstate macrosPaolo Bonzini1-251/+23
2025-01-23rust: pl011: switch vmstate to new-style macrosPaolo Bonzini3-19/+26
2025-01-23rust: qemu_api: add vmstate_structPaolo Bonzini1-0/+33
2025-01-23rust: vmstate: add public utility macros to implement VMStatePaolo Bonzini1-3/+58
2025-01-23rust: vmstate: implement VMState for scalar typesPaolo Bonzini1-2/+126
2025-01-23rust: vmstate: implement Zeroable for VMStateFieldPaolo Bonzini2-15/+34
2025-01-23rust: vmstate: add varray support to vmstate_of!Paolo Bonzini1-2/+40
2025-01-23rust: vmstate: implement VMState for non-leaf typesPaolo Bonzini1-1/+78
2025-01-23rust: vmstate: add new type safe implementationPaolo Bonzini2-6/+109
2025-01-23memattrs: Check the size of MemTxAttrsZhao Liu1-0/+2
2025-01-23memattrs: Convert unspecified member to boolZhao Liu1-7/+12
2025-01-23rust/pl011: Avoid bindings::*Zhao Liu1-3/+10
2025-01-23rust/qdev: Make REALIZE safeZhao Liu2-6/+6
2025-01-23stub: Fix build failure with --enable-user --disable-system --enable-toolsZhao Liu1-2/+2
2025-01-23docs: Add GNR, SRF and CWF CPU modelsTao Su1-4/+46
2025-01-23target/i386: Add new CPU model ClearwaterForestTao Su2-6/+162
2025-01-23target/i386: Export BHI_NO bit to guestsTao Su1-1/+1
2025-01-23target/i386: Introduce SierraForest-v2 modelTao Su1-0/+19
2025-01-23target/i386: avoid using s->tmp0 for add to implicit registersPaolo Bonzini1-7/+14
2025-01-23target/i386: extract common bits of gen_repz/gen_repz_nzPaolo Bonzini1-20/+14
2025-01-23target/i386: pull computation of string update value out of loopPaolo Bonzini1-28/+26
2025-01-23target/i386: execute multiple REP/REPZ iterations without leaving TBPaolo Bonzini1-6/+49
2025-01-23target/i386: optimize CX handling in repeated string operationsPaolo Bonzini1-1/+14
2025-01-23target/i386: do not use gen_op_jz_ecx for repeated string operationsPaolo Bonzini1-1/+2
2025-01-23target/i386: make cc_op handling more explicit for repeated string instructions.Paolo Bonzini1-3/+21
2025-01-23target/i386: fix RF handling for string instructionsPaolo Bonzini1-1/+21
2025-01-23target/i386: tcg: move gen_set/reset_* earlier in the filePaolo Bonzini1-40/+40
2025-01-23target/i386: reorganize ops emitted by do_gen_rep, drop repz_optPaolo Bonzini1-47/+13
2025-01-23target/i386: unify choice between single and repeated string instructionsPaolo Bonzini2-37/+17
2025-01-23target/i386: unify REP and REPZ/REPNZ generationPaolo Bonzini1-19/+20
2025-01-23target/i386: remove trailing 1 from gen_{j, cmov, set}cc1Paolo Bonzini2-12/+12
2025-01-23target/i386: inline gen_jcc into sole callerPaolo Bonzini2-9/+4
2025-01-22rust: pl011: fix repr(C) for PL011ClassPaolo Bonzini1-0/+1
2025-01-19hw/char/riscv_htif: Convert HTIF_DEBUG() to trace eventsPhilippe Mathieu-Daudé2-12/+7
2025-01-19target/riscv: Support Supm and Sspm as part of Zjpm v1.0Alexey Baturo2-0/+25
2025-01-19hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cacheJason Chien1-52/+153
2025-01-19target/riscv: Add Smdbltrp ISA extension enable switchClément Léger2-0/+12
2025-01-19target/riscv: Implement Smdbltrp behaviorClément Léger1-16/+41
2025-01-19target/riscv: Implement Smdbltrp sret, mret and mnret behaviorClément Léger1-0/+12