summary refs log tree commit diff stats
path: root/rust/qemu-api-macros/src/utils.rs (unfollow)
Commit message (Expand)AuthorFilesLines
2025-01-19target/riscv: Support Supm and Sspm as part of Zjpm v1.0Alexey Baturo2-0/+25
2025-01-19hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cacheJason Chien1-52/+153
2025-01-19target/riscv: Add Smdbltrp ISA extension enable switchClément Léger2-0/+12
2025-01-19target/riscv: Implement Smdbltrp behaviorClément Léger1-16/+41
2025-01-19target/riscv: Implement Smdbltrp sret, mret and mnret behaviorClément Léger1-0/+12
2025-01-19target/riscv: Add Smdbltrp CSRs handlingClément Léger4-0/+18
2025-01-19target/riscv: Add Ssdbltrp ISA extension enable switchClément Léger1-0/+2
2025-01-19target/riscv: Implement Ssdbltrp exception handlingClément Léger3-6/+39
2025-01-19target/riscv: Implement Ssdbltrp sret, mret and mnret behaviorClément Léger1-1/+34
2025-01-19target/riscv: Add Ssdbltrp CSRs handlingClément Léger5-12/+84
2025-01-19target/riscv: Fix henvcfg potentially containing stale bitsClément Léger1-2/+8
2025-01-19target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/SsccfgAtish Patra1-0/+4
2025-01-19target/riscv: Add implied rule for counter delegation extensionsAtish Patra1-1/+11
2025-01-19target/riscv: Invoke pmu init after feature enableAtish Patra1-14/+14
2025-01-19target/riscv: Add counter delegation/configuration supportKaiwen Xue1-12/+292
2025-01-19target/riscv: Add select value range check for counter delegationKaiwen Xue1-1/+35
2025-01-19target/riscv: Add counter delegation definitionsKaiwen Xue3-1/+9
2025-01-19target/riscv: Add properties for counter delegation ISA extensionsAtish Patra2-0/+4
2025-01-19target/riscv: Support generic CSR indirect accessKaiwen Xue2-6/+166
2025-01-19target/riscv: Enable S*stateen bits for AIAAtish Patra1-1/+84
2025-01-19target/riscv: Decouple AIA processing from xiselect and xiregKaiwen Xue1-26/+139
2025-01-19target/riscv: Add properties for Indirect CSR Access extensionKaiwen Xue2-0/+4
2025-01-19hw/riscv/virt: Remove unnecessary use of &first_cpuPhilippe Mathieu-Daudé1-1/+1
2025-01-19target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpuPhilippe Mathieu-Daudé3-4/+6
2025-01-19target/riscv: Add Zicfilp support for SmrnmiFrank Chang3-1/+20
2025-01-19target/riscv: Add Smrnmi cpu extensionTommy Wu2-0/+11
2025-01-19target/riscv: Add Smrnmi mnret instructionTommy Wu4-5/+64
2025-01-19target/riscv: Handle Smrnmi interrupt and exceptionTommy Wu6-7/+152
2025-01-19target/riscv: Add Smrnmi CSRsTommy Wu4-0/+105
2025-01-19target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfigTommy Wu1-0/+1
2025-01-19target/riscv: Enable updates for pointer masking variables and thus enable po...Alexey Baturo1-0/+6
2025-01-19target/riscv: Apply pointer masking for virtualized memory accessesAlexey Baturo5-29/+82
2025-01-19target/riscv: Update address modify functions to take into account pointer ma...Alexey Baturo2-6/+32
2025-01-19target/riscv: Add pointer masking tb flagsAlexey Baturo3-0/+11
2025-01-19target/riscv: Add helper functions to calculate current number of masked bits...Alexey Baturo2-0/+83
2025-01-19target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjp...Alexey Baturo6-5/+58
2025-01-19target/riscv: Remove obsolete pointer masking extension code.Alexey Baturo9-544/+19
2025-01-19target/riscv: add trace in riscv_raise_exception()Daniel Henrique Barboza2-0/+9
2025-01-19target/riscv: use RISCVException enum in exception helpersDaniel Henrique Barboza3-3/+5
2025-01-19target/riscv/tcg: add shaDaniel Henrique Barboza3-0/+11
2025-01-19target/riscv: add shgatpaDaniel Henrique Barboza2-0/+1
2025-01-19target/riscv: add shvsatpaDaniel Henrique Barboza2-0/+1
2025-01-19target/riscv: add shvstvecdDaniel Henrique Barboza2-0/+1
2025-01-19target/riscv: add shtvalaDaniel Henrique Barboza2-0/+1
2025-01-19target/riscv: add shvstvalaDaniel Henrique Barboza2-0/+1
2025-01-19target/riscv: add shcounterenwDaniel Henrique Barboza2-0/+1
2025-01-19riscv/gdbstub: add V bit to priv regYanfeng Liu1-4/+19
2025-01-19target/riscv: rvv: speed up small unit-stride loads and storesCraig Blackmore1-0/+16
2025-01-19target/riscv: rvv: fix typo in vext continuous ldst function namesCraig Blackmore1-5/+5
2025-01-17softfloat: Constify helpers returning float_status fieldPhilippe Mathieu-Daudé1-11/+14