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2025-07-04monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()Daniel Henrique Barboza1-2/+2
Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be logged by log_cpu_exec() in TCG. This flag was then used in commit b227f6a8a7 to print RISC-V vector registers using this flag. Note that this change was done in riscv_cpu_dump_state(), the cpu_dump_state() callback for RISC-V, the same callback used in hmp_info_registers(). Back then we forgot to change hmp_info_registers(), and 'info registers' isn't showing RISC-V vector registers as a result. No other target is impacted since only RISC-V is using CPU_DUMP_VPU. There's no reason to not show VPU regs in info_registers(), so add CPU_DUMP_VPU to hmp_info_registers(). This will print vector registers for all RISC-V machines and, as said above, has no impact in other archs. Cc: Dr. David Alan Gilbert <dave@treblig.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250623145306.991562-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-07-04accel/system: Convert pre_resume() from AccelOpsClass to AccelClassPhilippe Mathieu-Daudé7-7/+15
Accelerators call pre_resume() once. Since it isn't a method to call for each vCPU, move it from AccelOpsClass to AccelClass. Adapt WHPX. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250702185332.43650-21-philmd@linaro.org>
2025-07-04accel: Pass AccelState argument to gdbstub_supported_sstep_flags()Philippe Mathieu-Daudé5-5/+5
In order to have AccelClass methods instrospect their state, we need to pass AccelState by argument. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-37-philmd@linaro.org>
2025-07-04accel: Remove unused MachineState argument of AccelClass::setup_post()Philippe Mathieu-Daudé3-3/+3
This method only accesses xen_domid/xen_domid_restrict, which are both related to the 'accelerator', not the machine. Besides, xen_domid aims to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict QOM property. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-36-philmd@linaro.org>
2025-07-04accel: Directly pass AccelState argument to AccelClass::has_memory()Philippe Mathieu-Daudé3-4/+4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-34-philmd@linaro.org>
2025-07-04accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()Philippe Mathieu-Daudé1-5/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-35-philmd@linaro.org>
2025-07-04accel/kvm: Prefer local AccelState over global MachineState::accelPhilippe Mathieu-Daudé1-3/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-32-philmd@linaro.org>
2025-07-04accel/tcg: Prefer local AccelState over global current_accel()Philippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-33-philmd@linaro.org>
2025-07-04accel/hvf: Re-use QOM allocated statePhilippe Mathieu-Daudé1-3/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250606164418.98655-8-philmd@linaro.org>
2025-07-04accel: Propagate AccelState to AccelClass::init_machine()Philippe Mathieu-Daudé11-11/+11
In order to avoid init_machine() to call current_accel(), pass AccelState along. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-31-philmd@linaro.org>
2025-07-04accel: Keep reference to AccelOpsClass in AccelClassPhilippe Mathieu-Daudé4-3/+10
Allow dereferencing AccelOpsClass outside of accel/accel-system.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-30-philmd@linaro.org>
2025-07-04accel: Expose and register generic_handle_interrupt()Philippe Mathieu-Daudé8-6/+13
In order to dispatch over AccelOpsClass::handle_interrupt(), we need it always defined, not calling a hidden handler under the hood. Make AccelOpsClass::handle_interrupt() mandatory. Expose generic_handle_interrupt() prototype and register it for each accelerator. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Message-Id: <20250703173248.44995-29-philmd@linaro.org>
2025-07-04accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'Philippe Mathieu-Daudé6-5/+18
'dummy' helpers are specific to accelerator implementations, no need to expose them via "system/cpus.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-27-philmd@linaro.org>
2025-07-04accel/whpx: Expose whpx_enabled() to common codePhilippe Mathieu-Daudé5-17/+27
Currently whpx_enabled() is restricted to target-specific code. By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250703173248.44995-26-philmd@linaro.org>
2025-07-04accel/nvmm: Expose nvmm_enabled() to common codePhilippe Mathieu-Daudé5-18/+27
Currently nvmm_enabled() is restricted to target-specific code. By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-25-philmd@linaro.org>
2025-07-04accel/system: Document cpu_synchronize_state_post_init/reset()Philippe Mathieu-Daudé2-0/+16
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-24-philmd@linaro.org>
2025-07-04accel/system: Document cpu_synchronize_state()Philippe Mathieu-Daudé2-1/+18
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-23-philmd@linaro.org>
2025-07-04accel/kvm: Remove kvm_cpu_synchronize_state() stubPhilippe Mathieu-Daudé1-4/+0
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code to accel/kvm") the kvm_cpu_synchronize_state() stub is not necessary. Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-22-philmd@linaro.org>
2025-07-04accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty fieldPhilippe Mathieu-Daudé1-12/+11
No need for accel-specific @dirty field when we have a generic one in CPUState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-21-philmd@linaro.org>
2025-07-04accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty fieldPhilippe Mathieu-Daudé1-11/+10
No need for accel-specific @dirty field when we have a generic one in CPUState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-20-philmd@linaro.org>
2025-07-04accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty fieldPhilippe Mathieu-Daudé5-11/+10
No need for accel-specific @dirty field when we have a generic one in CPUState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Message-Id: <20250703173248.44995-19-philmd@linaro.org>
2025-07-04cpus: Document CPUState::vcpu_dirty fieldPhilippe Mathieu-Daudé1-1/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20250703173248.44995-18-philmd@linaro.org>
2025-07-04accel/hvf: Report missing com.apple.security.hypervisor entitlementPhilippe Mathieu-Daudé1-0/+5
We need the QEMU binary signed to be able to use HVF. Improve the following: $ ./qemu-system-aarch64-unsigned -M virt -accel hvf qemu-system-aarch64-unsigned: -accel hvf: Error: ret = HV_DENIED (0xfae94007, at ../../accel/hvf/hvf-accel-ops.c:339) Abort trap: 6 to: $ ./qemu-system-aarch64-unsigned -M virt -accel hvf qemu-system-aarch64-unsigned: -accel hvf: Could not access HVF. Is the executable signed with com.apple.security.hypervisor entitlement? Suggested-by: Shatyuka <shatyuka@qq.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2800 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Message-Id: <20250702185332.43650-29-philmd@linaro.org>
2025-07-04accel/hvf: Move generic method declarations to hvf-all.cPhilippe Mathieu-Daudé2-269/+271
hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL), while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-17-philmd@linaro.org>
2025-07-04accel/hvf: Move per-cpu method declarations to hvf-accel-ops.cPhilippe Mathieu-Daudé2-28/+30
hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL), while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-16-philmd@linaro.org>
2025-07-04accel/hvf: Restrict internal declarationsPhilippe Mathieu-Daudé2-38/+34
Common code only needs to know whether HVF is enabled and the QOM type. Move the rest to "hvf_int.h", removing the need for COMPILING_PER_TARGET #ifdef'ry. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-15-philmd@linaro.org>
2025-07-04accel/tcg: Unregister the RCU before exiting RR threadPhilippe Mathieu-Daudé1-0/+2
Although unreachable, still unregister the RCU before exiting the thread, as documented in "qemu/rcu.h": /* * Important ! * * Each thread containing read-side critical sections must be registered * with rcu_register_thread() before calling rcu_read_lock(). * rcu_unregister_thread() should be called before the thread exits. */ Unregister the RCU to be on par with what is done for other accelerators. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250702185332.43650-66-philmd@linaro.org>
2025-07-04accel/tcg: Clear exit_request once in tcg_cpu_exec()Philippe Mathieu-Daudé2-1/+3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250701144017.43487-62-philmd@linaro.org>
2025-07-04accel/tcg: Factor tcg_dump_stats() out for re-usePhilippe Mathieu-Daudé2-3/+10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-11-philmd@linaro.org>
2025-07-04accel/tcg: Factor tcg_dump_flush_info() outPhilippe Mathieu-Daudé1-10/+17
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-10-philmd@linaro.org>
2025-07-04accel/tcg: Remove profiler leftoverPhilippe Mathieu-Daudé1-6/+0
TCG profiler was removed in commit 1b65b4f54c7. Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-9-philmd@linaro.org>
2025-07-04accel/tcg: Remove 'info opcount' and @x-query-opcountPhilippe Mathieu-Daudé4-54/+0
Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER", released with QEMU v8.1.0) we get pointless output: (qemu) info opcount [TCG profiler not compiled] Remove that unstable and unuseful command. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-8-philmd@linaro.org>
2025-07-04accel/kvm: Reduce kvm_create_vcpu() declaration scopePhilippe Mathieu-Daudé2-9/+7
kvm_create_vcpu() is only used within the same file unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-7-philmd@linaro.org>
2025-07-04accel/kvm: Remove kvm_init_cpu_signals() stubPhilippe Mathieu-Daudé1-5/+0
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code to accel/kvm") the kvm_init_cpu_signals() stub is not necessary. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703173248.44995-6-philmd@linaro.org>
2025-07-04target: riscv: Add Svrsw60t59b extension supportAlexandre Ghiti7-3/+18
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Reviewed-by: Deepak Gupta <debug@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com> Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8530@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04target/riscv: Add a property to set vill bit on reserved usage of vsetvli ↵Vasilis Liaskovitis5-4/+16
instruction Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1 and rd arguments are x0. In this case, if the new property is true, only the vill bit will be set. See https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding According to the spec, the above use cases are reserved, and "Implementations may set vill in either case." Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2422 Signed-off-by: Vasilis Liaskovitis <vliaskovitis@suse.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250618213542.22873-1-vliaskovitis@suse.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04tests/tcg/riscv64: Add test for MEPC bit maskingCharalampos Mitrodimas2-0/+77
Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an illegal instruction exception, copies STVEC to MEPC in the trap handler, and verifies that MEPC masks bits [1:0] correctly for IALIGN=32. Without the fix, MEPC retains the mode bits (returns non-zero/FAIL). With the fix, MEPC clears bits [1:0] (returns 0/PASS). Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-3-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04target/riscv: Fix MEPC/SEPC bit masking for IALIGNCharalampos Mitrodimas3-6/+17
According to the RISC-V Privileged Architecture specification, the low bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits must be zero. This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and the implicit reads by MRET/SRET instructions to properly mask the lowest bit(s) based on whether the C extension is enabled: - When C extension is enabled (IALIGN=16): mask bit 0 - When C extension is disabled (IALIGN=32): mask bits [1:0] Previously, when vectored mode bits from STVEC (which sets bit 0 for vectored mode) were written to MEPC, the bits would not be cleared correctly, causing incorrect behavior on MRET. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2855 Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-2-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04migration: Fix migration failure when aia is configured as aplic-imsicliu.xuemei1@zte.com.cn2-4/+18
Address an error in migration when aia is configured as 'aplic-imsic' in riscv kvm vm by adding riscv_aplic_state_needed() and riscv_imsic_state_needed() to determine whether the corresponding sates are needed. Previously, the fields in the vmsds of 'riscv_aplic' and 'riscv_imsic' can only be initialized under certain special conditions in commit 95a97b3fd2. However, the corresponding ses of these vmsds are inserted into the savevm_state.handlers unconditionally. This led to migration failure characterized by uninitialized fields when save vm state: qemu-system-riscv64: ../migration/vmstate.c:433: vmstate_save_state_v: Assertion 'first_elem || !n_elems || !size' failed. Fixes: 95a97b3fd2 ("target/riscv: update APLIC and IMSIC to support KVM AIA") Signed-off-by: Xuemei Liu <liu.xuemei1@zte.com.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250616150034827wuHs_ffe3Qm8cqFXT7HeW@zte.com.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04target/riscv: rvv: Fix missing exit TB flow for ldff_transMax Chou1-0/+6
According to the V spec, the vector fault-only-first load instructions may change the VL CSR. So the ldff_trans TCG translation function should generate the lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to make sure the vl_eq_vlmax TB flag is correct. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250627133013.443997-1-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototypeHuang Borong8-0/+346
This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn> Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Signed-off-by: Yu Hu <819258943@qq.com> Signed-off-by: Ran Wang <wangran@bosc.ac.cn> Signed-off-by: Borong Huang <3543977024@qq.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04target/riscv: Add BOSC's Xiangshan Kunminghu CPUHuang Borong2-0/+59
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source, high-performance RISC-V processor. More details can be found at: https://github.com/OpenXiangShan/XiangShan Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized based on four RISC-V specifications: Volume I: Unprivileged Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The extensions within each category are organized according to the chapter order in the specifications. Signed-off-by: Yu Hu <huyu@bosc.ac.cn> Signed-off-by: Ran Wang <wangran@bosc.ac.cn> Signed-off-by: Borong Huang <3543977024@qq.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250425122212.364-1-wangran@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for pcieJoel Stanley1-2/+2
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-13-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for iommuJoel Stanley1-2/+1
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-12-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for rtcJoel Stanley1-2/+3
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-11-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for uartJoel Stanley1-3/+3
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-10-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for resetJoel Stanley1-2/+3
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-9-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for virtioJoel Stanley1-3/+1
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-8-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for plicJoel Stanley1-2/+2
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-7-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/riscv/virt: Use setprop_sized_cells for aclintJoel Stanley1-9/+9
The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250604025450.85327-6-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>