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2025-05-06hw/arm/virt: Remove deprecated virt-3.1 machinePhilippe Mathieu-Daudé1-7/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429153907.31866-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-3.0 machinePhilippe Mathieu-Daudé1-7/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429153907.31866-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Update comment about Multiprocessor Affinity RegisterPhilippe Mathieu-Daudé1-6/+1
Support on ARMv7 has been dropped in commit 82bf7ae84ce ("target/arm: Remove KVM support for 32-bit Arm hosts"). Update the comment in virt_cpu_mp_affinity() to avoid mentioning it. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429153907.31866-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/gpio/imx_gpio: Fix interpretation of GDIR polarityBernhard Beschow1-1/+1
According to the i.MX 8M Plus reference manual, a GPIO pin is configured as an output when the corresponding bit in the GDIR register is set. The function imx_gpio_set_int_line() is intended to be a no-op if the pin is configured as an output, returning early in such cases. However, it inverts the condition. Fix this by returning early when the bit is set. cc: qemu-stable@nongnu.org Fixes: f44272809779 ("i.MX: Add GPIO device") Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250501183445.2389-4-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/pci-host/designware: Fix viewport configurationBernhard Beschow1-2/+2
Commit 6970f91ac781, "hw/pci-host/designware: Use deposit/extract API" accidentally introduced a copy-and-paste error, causing Linux 6.14 to hang when initializing the PCIe bridge on the imx8mp-evk machine. This fix corrects the error. Fixes: 6970f91ac781 ("hw/pci-host/designware: Use deposit/extract API") Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250501183445.2389-3-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/pci-host/designware: Remove unused includeBernhard Beschow1-1/+0
The DEFINE_TYPES() macro doesn't need the qemu/module.h include. Fixes: 13a07eb146c8 ("hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macro") Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250501183445.2389-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGETPeter Maydell3-53/+9
Our KVM code includes backwards compatibility support for ancient kernels which don't support the KVM_ARM_PREFERRED_TARGET ioctl. This ioctl was introduced in kernel commit 42c4e0c77ac91 in September 2013 and is in v3.12, so it's reasonable to assume it's present. (We already dropped support for kernels without KVM_CAP_DEVICE_CTRL, a feature added to the kernel in April 2013, in our commit 84f298ea3e; so there are only about six months' worth of kernels, from v3.9 to v3.11, that we don't already fail to run on and that this commit is dropping handling for.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250318114222.1018200-1-peter.maydell@linaro.org
2025-05-06docs: Don't define duplicate label in qemu-block-drivers.rst.incPeter Maydell2-3/+1
Sphinx requires that labels within documents are unique across the whole manual. This is because the "create a hyperlink" directive specifies only the name of the label, not a filename+label. Some Sphinx versions will warn about duplicate labels, but even if there is no warning there is still an ambiguity and no guarantee that the hyperlink will be created to the right target. For QEMU this is awkward, because we have various .rst.inc fragments which we include into multiple .rst files. If you define a label in the .rst.inc file then it will be a duplicate label. We have mostly worked around this by not putting labels into those .rst.inc files, or by adding "insert a label" functionality into the hxtool extension (see commit 1eeb432a953b0 "doc/sphinx/hxtool.py: add optional label argument to SRST directive"). Unfortunately in commit 7f6314427e78 ("docs/devel: add a codebase section") we accidentally added a duplicate label, because not all Sphinx versions warn about the mistake. In this case the link was only from the developer docs codebase summary, so as the simplest fix for the stable branch, we drop the link entirely. Cc: qemu-stable@nongnu.org Fixes: 1eeb432a953b0 "doc/sphinx/hxtool.py: add optional label argument to SRST directive" Reported-by: Dario Faggioli <dfaggioli@suse.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Eric Blake <eblake@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250501093126.716667-1-peter.maydell@linaro.org
2025-05-06target/arm: Don't assert() for ISB/SB inside IT blockPeter Maydell1-1/+2
If the guest code has an ISB or SB insn inside an IT block, we generate incorrect code which trips a TCG assertion: qemu-system-arm: ../tcg/tcg-op.c:3343: void tcg_gen_goto_tb(unsigned int): Assertion `(tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0' failed. This is because we call gen_goto_tb(dc, 1, ...) twice: brcond_i32 ZF,$0x0,ne,$L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x73d948001b81 set_label $L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x73d948001b81 Both calls are in arm_tr_tb_stop(), one for the DISAS_NEXT/DISAS_TOO_MANY handling, and one for the dc->condjump condition-failed codepath. The DISAS_NEXT handling doesn't have this problem because arm_post_translate_insn() does the handling of "emit the label for the condition-failed conditional execution" and so arm_tr_tb_stop() doesn't have dc->condjump set. But for DISAS_TOO_MANY we don't do that. Fix the bug by making arm_post_translate_insn() handle the DISAS_TOO_MANY case. This only affects the SB and ISB insns when used in Thumb mode inside an IT block: only these insns specifically set is_jmp to TOO_MANY, and their A32 encodings are unconditional. For the major TOO_MANY case (breaking the TB because it would cross a page boundary) we do that check and set is_jmp to TOO_MANY only after the call to arm_post_translate_insn(); so arm_post_translate_insn() sees is_jmp == DISAS_NEXT, and we emit the correct code for that situation. With this fix we generate the somewhat more sensible set of TCG ops: brcond_i32 ZF,$0x0,ne,$L1 set_label $L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x7c5434001b81 (NB: the TCG optimizer doesn't optimize out the jump-to-next, but we can't really avoid emitting it because we don't know at the point we're emitting the handling for the condexec check whether this insn is going to happen to be a nop for us or not.) Cc: qemu-stable@nongnu.org Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2942 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250501125544.727038-1-peter.maydell@linaro.org
2025-05-06hw/arm: Attach PSPI module to NPCM8XX SoCTim Lee2-1/+12
Nuvoton's PSPI is a general purpose SPI module which enables connections to SPI-based peripheral devices. Attach it to the NPCM8XX. Tested: NPCM8XX PSPI driver probed successfully from dmesg log. Signed-off-by: Tim Lee <timlee660101@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20250414020629.1867106-1-timlee660101@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06tests/functional: Add test for imx8mp-evk board with USDHC coverageBernhard Beschow3-0/+70
Introduce a functional test which boots Debian 12 on the imx8mp-evk board. Since the root filesystem resides on an SD card, the test also verifies the basic operation of the USDHC. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250409202630.19667-1-shentey@gmail.com [PMM: added extra blank line as suggested by thuth; set timeout to 240s] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam fieldPhilippe Mathieu-Daudé2-2/+1
The VirtMachineClass::no_highmem_ecam field was only used by virt-2.12 machine, which got removed. Remove it and simplify virt_instance_init(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.12 machinePhilippe Mathieu-Daudé1-11/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver fieldPhilippe Mathieu-Daudé2-4/+1
The VirtMachineClass::smbios_old_sys_ver field was only used by virt-2.11 machine, which got removed. Remove it and simplify virt_build_smbios(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.11 machinePhilippe Mathieu-Daudé1-10/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.10 machinePhilippe Mathieu-Daudé1-9/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.9 machinePhilippe Mathieu-Daudé1-7/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers fieldPhilippe Mathieu-Daudé3-10/+1
The VirtMachineClass::claim_edge_triggered_timers field was only used by virt-2.8 machine, which got removed. Remove it and simplify fdt_add_timer_nodes() and build_gtdt(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.8 machinePhilippe Mathieu-Daudé1-13/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove VirtMachineClass::no_its fieldPhilippe Mathieu-Daudé3-14/+8
The VirtMachineClass::no_its field was only used by virt-2.7 machine, which got removed. Remove it and simplify virt_instance_init() and virt_acpi_build(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.7 machinePhilippe Mathieu-Daudé1-13/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustmentPhilippe Mathieu-Daudé2-17/+15
The VirtMachineClass::disallow_affinity_adjustment field was only used by virt-2.6 machine, which got removed. Remove it and simplify virt_cpu_mp_affinity(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> [PMM: Remove now-unused variable] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove VirtMachineClass::no_pmu fieldPhilippe Mathieu-Daudé2-5/+0
The VirtMachineClass::no_pmu field was only used by virt-2.6 machine, which got removed. Remove it and simplify machvirt_init(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/virt: Remove deprecated virt-2.6 machinePhilippe Mathieu-Daudé1-12/+0
This machine has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") it can now be removed. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debugPierrick Bouvier1-1/+21
It was reported that QEMU monitor command gva2gpa was reporting unmapped memory for a valid access (qemu-system-aarch64), during a copy from kernel to user space (__arch_copy_to_user symbol in Linux) [1]. This was affecting cpu_memory_rw_debug also, which is used in numerous places in our codebase. After investigating, the problem was specific to arm_cpu_get_phys_page_attrs_debug. When performing user access from a privileged space, we need to do a second lookup for user mmu idx, following what get_a64_user_mem_index is doing at translation time. [1] https://lists.nongnu.org/archive/html/qemu-discuss/2025-04/msg00013.html Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: extract arm_cpu_get_phys_pagePierrick Bouvier1-10/+14
Allow to call that function easily several times in next commit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: get current security_space for current mmu_idxPierrick Bouvier1-1/+1
It should be equivalent to previous code. Allow to call common function to get a page address later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: extract arm_mmu_idx_to_security_spacePierrick Bouvier1-7/+14
We'll reuse this function later. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hvf: only update sysreg from owning threadMads Ynddal1-1/+6
hv_vcpu_set_sys_reg should only be called from the owning thread of the vCPU, so to avoid crashes, the call to hvf_update_guest_debug is dispatched to the individual threads. Tested-by: Daniel Gomez <da.gomez@samsung.com> Signed-off-by: Mads Ynddal <m.ynddal@samsung.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250402135229.28143-3-mads@ynddal.dk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hvf: avoid repeatedly setting trap debug for each cpuMads Ynddal1-16/+11
hvf_arch_set_traps is already called from a context of a specific CPUState, so we don't need to do a nested CPU_FOREACH. It also results in an error from hv_vcpu_set_sys_reg, as it may only be called from the thread owning the vCPU. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2895 Tested-by: Daniel Gomez <da.gomez@samsung.com> Signed-off-by: Mads Ynddal <m.ynddal@samsung.com> Reported-by: Daniel Gomez <da.gomez@samsung.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250402135229.28143-2-mads@ynddal.dk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoCTim Lee1-1/+1
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals. Correct the `valid_cpu_types` setting to match the NPCM8XX SoC. Cc: qemu-stable@nongnu.org Fixes: 7e70eb3cad7c83 ("hw/arm: Add NPCM845 Evaluation board") Signed-off-by: Tim Lee <timlee660101@gmail.com> Message-id: 20250428022934.3081139-1-timlee660101@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hw/loongarch/virt: Allow user to customize OEM ID and OEM table IDBibo Mao1-0/+58
On LoongArch virt machine, the default OEM ID and OEM table ID is "BOCHS " and "BXPC ". Here property x-oem-id and x-oem-table-id is added on virt machine to set customized OEM ID and OEM table ID. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/loongarch/virt: Replace RSDT with XSDT tableBibo Mao1-6/+6
XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit address in the table. There is LoongArch system support from ACPI Specification 6.4 and later, XSDT is supported by LoongArch system. Here replace RSDT with XSDT table. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/loongarch/virt: Get physical entry address with elf fileBibo Mao2-1/+2
With load_elf() api, image load low address and high address is converted to physical address if parameter translate_fn is provided. However executing entry address is still virtual address. Here convert entry address into physical address, since MMU is disabled when system power on, the first PC instruction should be physical address. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_pch: Replace legacy reset callback with new apiBibo Mao2-18/+9
Replace legacy reset callback register device_class_set_legacy_reset() with new function resettable_class_set_parent_phases(). With new API, it will call reset callback of parent object. The internal state has been cleared in parent object LOONGARCH_PIC_COMMON, here parent_phases.hold() is directly called. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_pch: Add reset supportBibo Mao2-0/+26
Add reset support with LoongArch pci irqchip, and register reset callback support with new API resettable_class_set_parent_phases(). Clear internal HW registers and SW state when virt machine resets. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_extioi: Replace legacy reset callback with new apiBibo Mao2-4/+9
Replace legacy reset callback register device_class_set_legacy_reset() with new function resettable_class_set_parent_phases(). With new API, it will call reset callback of parent object and then itself. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_extioi: Add reset supportBibo Mao2-0/+42
Add reset support with extioi irqchip, and register reset callback support with new API resettable_class_set_parent_phases(). Clear internal HW registers and SW state when virt machine resets. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_ipi: Add reset supportBibo Mao2-0/+30
Add reset support with ipi object, register reset callback and clear internal registers when virt machine resets. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-05accel/tcg: Build user-exec.c onceRichard Henderson2-7/+3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Avoid abi_ptr in user-exec.cRichard Henderson1-6/+16
In page_dump/dump_region, use guest_addr_max to check the size of the guest address space and size the output appropriately. This will change output with small values of -R reserved_va, but shouldn't affect anything else. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Remove TARGET_PAGE_DATA_SIZERichard Henderson4-19/+23
This macro is used by only one target, and even then under unusual conditions -- AArch64 with mmap's PROT_MTE flag. Since page size for aarch64-linux-user is variable, the per-page data size is also variable. Since page_reset_target_data via target_munmap does not have ready access to CPUState, simply pass in the size from the first allocation and remember that. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addrRichard Henderson5-41/+40
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05include/user: Use vaddr in guest-host.hRichard Henderson1-7/+7
Replace abi_ptr and abi_ulong with vaddr. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05include/user: Convert GUEST_ADDR_MAX to a variableRichard Henderson4-22/+25
Remove GUEST_ADDR_MAX and add guest_addr_max. Initialize it in *-user/main.c, after reserved_va. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Build cputlb.c onceRichard Henderson2-5/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Use vaddr for plugin_{load,store}_cbRichard Henderson1-2/+2
Avoid the use of abi_ptr within ldst_common.c.inc. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Use target_long_bits() in cputlb.cRichard Henderson1-12/+13
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Move tlb_vaddr_to_host declaration to probe.hRichard Henderson2-16/+16
This is a probing function, not a load/store function. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Move user-only tlb_vaddr_to_host out of lineRichard Henderson2-8/+6
At the same time, fix a mis-match between user and system by using vaddr not abi_ptr for the address parameter. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>