summary refs log tree commit diff stats
path: root/rust/qemu-api-macros/src (unfollow)
Commit message (Collapse)AuthorFilesLines
2025-05-29tests/functional: Add a test for the Stellaris arm machinesThomas Huth3-0/+50
The 2023 edition of the QEMU advent calendar featured an image that we can use to test whether the lm3s6965evb machine is basically still working. And for the lm3s811evb there is a small test kernel on github which can be used to check its UART. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20250519170242.520805-1-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/hvf: Include missing 'cpu-qom.h' headerPhilippe Mathieu-Daudé1-1/+1
ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU' 23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250513173928.77376-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/kvm: Include missing 'cpu-qom.h' headerPhilippe Mathieu-Daudé1-0/+1
ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU' 54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level); | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250513173928.77376-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/qmp: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier 'ARM_MAX_VQ' 83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250513173928.77376-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/cpu-features: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
"target/arm/cpu-features.h" dereferences the ARMISARegisters structure, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: In file included from target/arm/internals.h:33: target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters' 45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) | ^ target/arm/cpu-features.h:47:12: error: use of undeclared identifier 'R_ID_ISAR0_DIVIDE_SHIFT' 47 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250513173928.77376-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29hw/arm/boot: Include missing 'system/memory.h' headerPhilippe Mathieu-Daudé1-0/+1
default_reset_secondary() uses address_space_stl_notdirty(), itself declared in "system/memory.h". Include this header in order to avoid when refactoring headers: ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-function-declaration] address_space_stl_notdirty(as, info->smp_bootreg_addr, ^ Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250513173928.77376-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/cpregs: Include missing 'target/arm/cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
CPReadFn type definitions use the CPUARMState type, itself declared in "cpu.h". Include this file in order to avoid when refactoring headers: ../target/arm/cpregs.h:241:27: error: unknown type name 'CPUARMState' typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); ^ Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250513173928.77376-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm: Only link with zlib when TCG is enabledPhilippe Mathieu-Daudé2-1/+2
Since commit 538b764d341 ("target/arm: Move minor arithmetic helpers out of helper.c") we only use the zlib helpers under TCG. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250513173928.77376-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/hvf_arm: Avoid using poisoned CONFIG_HVF definitionPhilippe Mathieu-Daudé4-16/+22
In order to allow non-target specific code to include "hvf_arm.h", define the stubs in hvf-stub.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250513173928.77376-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29target/arm/tcg-stubs: compile file once (system)Philippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250513173928.77376-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29docs/interop: convert text files to restructuredTextSouleymane Conte5-81/+113
buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Souleymane Conte <conte.souleymane@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20250522092622.40869-1-conte.souleymane@gmail.com [PMM: switched a few more bits of formatting to monospaced; updated references to qcow2.txt in MAINTAINERS, qcow2-cache.txt and bitmaps.rst] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29hw/arm: Add missing psci_conduit to NPCM8XX SoC boot infoGuenter Roeck1-0/+1
Without psci_conduit, the Linux kernel crashes almost immediately. psci: probing for conduit method from DT. Internal error: Oops - Undefined instruction: 0000000002000000 [#1] PREEMPT SMP Fixes: ae0c4d1a1290 ("hw/arm: Add NPCM8XX SoC") Cc: qemu-stable@nongnu.org Cc: Hao Wu <wuhaotsh@google.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20250315142050.3642741-1-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29tests/qtest: Migrate GMAC test from 7xx to 8xxNabih Estefan2-5/+86
For upstreaming we migrated this test to 7xx (since that was already upstream) move it back to 8xx where it can check the 4 GMACs since that is the board this test was originally created for. Signed-off-by: Nabih Estefan <nabihestefan@google.com> Message-id: 20250508220718.735415-3-nabihestefan@google.com Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-29hw/arm: Add GMAC devices to NPCM8XX SoCHao Wu2-6/+53
The GMAC was originally created for the 8xx machine. During upstreaming both the GMAC and the 8XX we removed it so they would not depend on each other for the process, that connection should be added back in. Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Message-id: 20250508220718.735415-2-nabihestefan@google.com Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-28qapi: use imperative style in documentationPierrick Bouvier12-26/+26
As requested by Markus: > We prefer imperative mood "Return" over "Returns". Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-14-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Change several more]
2025-05-28qapi: make all generated files commonPierrick Bouvier1-19/+4
Monolithic files (qapi_nonmodule_outputs) can now be compiled just once, so we can remove qapi_util_outputs logic. This removes the need for any specific_ss file. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-13-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: remove qapi_specific_outputs from meson.buildPierrick Bouvier1-8/+3
There is no more QAPI files that need to be compiled per target, so we can remove this. qapi_specific_outputs is now empty, so we can remove the associated logic in meson. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-12-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make s390x specific CPU commands unconditionally availableDaniel P. Berrangé8-15/+35
This removes the TARGET_S390X and CONFIG_KVM conditions from the CPU commands that are conceptually specific to s390x. Top level stubs are provided to cope with non-s390x targets, or builds without KVM. The removal of CONFIG_KVM is justified by the fact there is no conceptual difference between running 'qemu-system-s390x -accel tcg' on a build with and without KVM built-in, so apps only using TCG can't rely on the CONFIG_KVM in the schema. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-11-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make most CPU commands unconditionally availableDaniel P. Berrangé14-406/+437
This removes the TARGET_* conditions from all the CPU commands that are conceptually target independent. Top level stubs are provided to cope with targets which do not currently implement all of the commands. Adjust the doc comments accordingly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-10-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: Make CpuModelExpansionInfo::deprecated-props optional and genericPhilippe Mathieu-Daudé1-4/+3
We'd like to have some unified QAPI schema. Having a structure field conditional to a target being built in is not very practical. While @deprecated-props is only used by s390x target, it is generic enough and could be used by other targets (assuming we expand CpuModelExpansionType enum values). Let's always include this field, regardless of the target, but make it optional. This is not a compatibility break only because the field remains present always on S390x. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-9-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: remove the misc-target.json fileDaniel P. Berrangé5-7/+0
This file is now empty and can thus be removed. Observe the pre-existing bug with s390-skeys.c and target/i386/monitor.c both including qapi-commands-misc-target.h despite not requiring it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-8-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make Xen event commands unconditionally availableDaniel P. Berrangé6-125/+125
This removes the TARGET_I386 condition from the Xen event channel commands, moving them to the recently introduced misc-i386.json QAPI file, given they are inherantly i386 specific commands. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-7-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make SGX commands unconditionally availableDaniel P. Berrangé6-81/+97
This removes the TARGET_I386 condition from the SGX confidential virtualization commands, moving them to the recently introduced misc-i386.json QAPI file, given they are inherantly i386 specific commands. Observe a pre-existing bug that the "SGXEPCSection" struct lacked a TARGET_I386 condition, despite its only usage being behind a TARGET_I386 condition. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-6-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: expose query-gic-capability command unconditionallyDaniel P. Berrangé7-45/+65
This removes the TARGET_ARM condition from the query-gic-capability command. This requires providing a QMP command stub for non-ARM targets. This in turn requires moving the command out of misc-target.json, since that will trigger symbol poisoning errors when built from target independent code. Following the earlier precedent, this creates a misc-arm.json file to hold this ARM specific command. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-5-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make SEV commands unconditionally availableDaniel P. Berrangé6-324/+316
This removes the TARGET_I386 condition from the SEV confidential virtualization commands, moving them to the recently introduced misc-i386.json QAPI file, given they are inherantly i386 specific commands. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-4-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: expand docs for SEV commandsDaniel P. Berrangé1-7/+43
This gives some more context about the behaviour of the commands in unsupported guest configuration or platform scenarios. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-3-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Tweak query-sev doc, turn error descriptions into Errors sections, delate a stray #, normalize whitespace, wrap lines]
2025-05-28qapi: expose rtc-reset-reinjection command unconditionallyDaniel P. Berrangé7-18/+40
This removes the TARGET_I386 condition from the rtc-reset-reinjection command. This requires providing a QMP command stub for non-i386 target. This in turn requires moving the command out of misc-target.json, since that will trigger symbol poisoning errors when built from target independent code. Rather than putting the command into misc.json, it is proposed to create misc-$TARGET.json files to hold commands whose impl is conceptually only applicable to a single target. This gives an obvious docs hint to consumers that the command is only useful in relation a specific target, while misc.json is for commands applicable to 2 or more targets. The current impl of qmp_rtc_reset_reinject() is a no-op if the i386 RTC is disabled in Kconfig, or if the running machine type lack any RTC device. The stub impl for non-i386 targets retains this no-op behaviour. However, it is now reporting an Error mentioning this command is not available for current target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-2-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28accel/tcg: Assert TCGCPUOps.pointer_wrap is setRichard Henderson2-5/+3
All targets now provide the function, so we can make the call unconditional. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/sparc: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+13
Check address masking state for sparc64. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/s390x: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+9
Use the existing wrap_address function. Cc: qemu-s390x@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/riscv: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+26
Check 32 vs 64-bit and pointer masking state. Cc: qemu-riscv@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/ppc: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check 32 vs 64-bit state. Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/mips: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+9
Check 32 vs 64-bit addressing state. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/loongarch: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check va32 state. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/i386: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check 32 vs 64-bit state. Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/arm: Fill in TCGCPUOps.pointer_wrapRichard Henderson2-0/+25
For a-profile, check A32 vs A64 state. For m-profile, use cpu_pointer_wrap_uint32. Cc: qemu-arm@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target: Use cpu_pointer_wrap_uint32 for 32-bit targetsRichard Henderson9-0/+19
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are all 32-bit targets. AVR is more complicated, but using a 32-bit wrap preserves current behaviour. Cc: Michael Rolnik <mrolnik@gmail.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Stafford Horne <shorne@gmail.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Max Filippov <jcmvbkbc@gmail.com> Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target: Use cpu_pointer_wrap_notreached for strict align targetsRichard Henderson5-0/+21
Alpha, HPPA, and SH4 always use aligned addresses, and therefore never produce accesses that cross pages. Cc: Helge Deller <deller@gmx.de> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28accel/tcg: Add TCGCPUOps.pointer_wrapRichard Henderson2-0/+13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/sh4: Use MO_ALIGN for system UNALIGN()Richard Henderson1-1/+1
This should have been done before removing TARGET_ALIGNED_ONLY, as we did for hppa and alpha. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Fixes: 8244189419f9 ("target/sh4: Remove TARGET_ALIGNED_ONLY") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28tcg: Drop TCGContext.page_{mask,bits}Richard Henderson14-36/+31
Use exec/target_page.h instead of independent variables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28tcg: Drop TCGContext.tlb_dyn_max_bitsRichard Henderson4-12/+3
This was an extremely minor optimization for aarch64 and x86_64, to use a 32-bit AND instruction when the guest softmmu tlb maximum was sufficiently small. Both hosts can simply use a 64-bit AND insn instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Simplify compute_ldst_addr_type{a,b}Richard Henderson1-13/+13
Require TCGv_i32 and TCGv be identical, so drop the extensions. Return constants when possible instead of a mov into a temporary. Return register inputs unchanged when possible. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Drop DisasContext.r0Richard Henderson1-22/+2
Return a constant 0 from reg_for_read, and a new temporary from reg_for_write. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Use TARGET_LONG_BITS == 32 for system modeRichard Henderson2-6/+2
Now that the extended address instructions are handled separately from virtual addresses, we can narrow the emulation to 32-bit. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Fix printf format in mmu_translateRichard Henderson1-1/+2
Use TARGET_FMT_lx to match the target_ulong type of vaddr. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Use TCGv_i64 for compute_ldst_addr_eaRichard Henderson1-12/+12
Use an explicit 64-bit type for extended addresses. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Use uint64_t for CPUMBState.earRichard Henderson2-2/+2
Use an explicit 64-bit type for EAR. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Implement extended address load/store out of lineRichard Henderson3-12/+90
Use helpers and address_space_ld/st instead of inline loads and stores. This allows us to perform operations on physical addresses wider than virtual addresses. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Split out mb_transaction_failed_internalRichard Henderson1-28/+42
Use an explicit 64-bit type for the address to store in EAR. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>