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path: root/rust/qemu-api/src/assertions.rs (unfollow)
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2025-05-20target/riscv: convert TT Ascalon to RISCVCPUDefPaolo Bonzini1-67/+60
2025-05-20target/riscv: convert THead C906 to RISCVCPUDefPaolo Bonzini1-33/+28
2025-05-20target/riscv: generalize custom CSR functionalityPaolo Bonzini4-23/+40
2025-05-20target/riscv: th: make CSR insertion test a bit more intuitivePaolo Bonzini1-9/+4
2025-05-20target/riscv: convert SiFive U models to RISCVCPUDefPaolo Bonzini2-43/+37
2025-05-20target/riscv: convert ibex CPU models to RISCVCPUDefPaolo Bonzini1-23/+16
2025-05-20target/riscv: convert SiFive E CPU models to RISCVCPUDefPaolo Bonzini2-54/+21
2025-05-20target/riscv: convert dynamic CPU models to RISCVCPUDefPaolo Bonzini1-82/+31
2025-05-20target/riscv: convert bare CPU models to RISCVCPUDefPaolo Bonzini1-41/+17
2025-05-20target/riscv: convert profile CPU models to RISCVCPUDefPaolo Bonzini2-38/+48
2025-05-20target/riscv: convert abstract CPU classes to RISCVCPUDefPaolo Bonzini2-48/+46
2025-05-20target/riscv: add more RISCVCPUDef fieldsPaolo Bonzini3-1/+51
2025-05-20target/riscv: include default value in cpu_cfg_fields.h.incPaolo Bonzini2-12/+12
2025-05-20target/riscv: move RISCVCPUConfig fields to a header filePaolo Bonzini2-160/+173
2025-05-20target/riscv: merge riscv_cpu_class_init with the class_base functionPaolo Bonzini1-11/+10
2025-05-20target/riscv: store RISCVCPUDef struct directly in the classPaolo Bonzini8-29/+39
2025-05-20target/riscv: introduce RISCVCPUDefPaolo Bonzini2-9/+22
2025-05-20target/riscv: move satp_mode.{map,init} out of CPUConfigPaolo Bonzini3-30/+30
2025-05-20target/riscv: remove supported from RISCVSATPMapPaolo Bonzini2-11/+23
2025-05-20target/riscv: update max_satp_mode based on QOM propertiesPaolo Bonzini5-32/+24
2025-05-20target/riscv: cpu: store max SATP mode as a single integerPaolo Bonzini3-7/+8
2025-05-20target/riscv: assert argument to set_satp_mode_max_supported is validPaolo Bonzini1-1/+5
2025-05-20hw/riscv: acpi: only create RHCT MMU entry for supported typesPaolo Bonzini1-3/+6
2025-05-20qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabili...Zhao Liu1-2/+2
2025-05-20qapi/misc-target: Fix the doc related SGXEPCSectionZhao Liu1-2/+2
2025-05-20qapi/misc-target: Rename SGXInfo to SgxInfoZhao Liu3-15/+15
2025-05-20qapi/misc-target: Rename SGXEPCSection to SgxEpcSectionZhao Liu2-12/+12
2025-05-20hw/pci-host: Remove unused pci_host_data_be_opsRakesh Jeyasingh3-11/+0
2025-05-20hw/pci-host/gt64120: Fix endianness handlingRakesh Jeyasingh1-34/+48
2025-05-20i386/hvf: Make CPUID_HT supportedXiaoyao Li1-1/+1
2025-05-20i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supportedXiaoyao Li1-3/+5
2025-05-19hw/riscv/virt.c: remove 'long' casts in fmt stringsDaniel Henrique Barboza1-15/+17
2025-05-19hw/riscv/virt.c: use s->memmap in finalize_fdt() functionsDaniel Henrique Barboza1-22/+22
2025-05-19hw/riscv/virt.c: use s->memmap in create_fdt_virtio()Daniel Henrique Barboza1-7/+10
2025-05-19hw/riscv/virt.c: use s->memmap in create_fdt_sockets() pathDaniel Henrique Barboza1-42/+47
2025-05-19hw/riscv/virt.c: use s->memmap in create_fdt() pathDaniel Henrique Barboza1-9/+10
2025-05-19hw/riscv/virt.c: add 'base' arg in create_fw_cfg()Daniel Henrique Barboza1-3/+2
2025-05-19hw/riscv/virt.c: use s->memmap in virt_machine_done()Daniel Henrique Barboza1-8/+7
2025-05-19hw/riscv/virt.c: remove trivial virt_memmap referencesDaniel Henrique Barboza1-15/+14
2025-05-19hw/riscv/virt.c: enforce s->memmap use in machine_init()Daniel Henrique Barboza1-27/+27
2025-05-19target/riscv/kvm: add scounteren CSRDaniel Henrique Barboza1-0/+2
2025-05-19target/riscv/kvm: read/write KVM regs via env sizeDaniel Henrique Barboza1-5/+7
2025-05-19target/riscv/kvm: add senvcfg CSRDaniel Henrique Barboza1-0/+2
2025-05-19target/riscv/kvm: do not read unavailable CSRsDaniel Henrique Barboza1-3/+59
2025-05-19target/riscv/kvm: add kvm_csr_cfgs[]Daniel Henrique Barboza2-36/+86
2025-05-19target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macroDaniel Henrique Barboza1-58/+41
2025-05-19target/riscv/kvm: turn u32/u64 reg functions into macrosDaniel Henrique Barboza1-13/+9
2025-05-19target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()Daniel Henrique Barboza1-1/+1
2025-05-19target/riscv/kvm: minor fixes/tweaksDaniel Henrique Barboza1-15/+14
2025-05-19target/riscv: Fix write_misa vs aligned next_pcRichard Henderson1-5/+17