focaccia-qemu - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Files	Lines
2025-01-23	stub: Fix build failure with --enable-user --disable-system --enable-tools	Zhao Liu	1	-2/+2
2025-01-23	docs: Add GNR, SRF and CWF CPU models	Tao Su	1	-4/+46
2025-01-23	target/i386: Add new CPU model ClearwaterForest	Tao Su	2	-6/+162
2025-01-23	target/i386: Export BHI_NO bit to guests	Tao Su	1	-1/+1
2025-01-23	target/i386: Introduce SierraForest-v2 model	Tao Su	1	-0/+19
2025-01-23	target/i386: avoid using s->tmp0 for add to implicit registers	Paolo Bonzini	1	-7/+14
2025-01-23	target/i386: extract common bits of gen_repz/gen_repz_nz	Paolo Bonzini	1	-20/+14
2025-01-23	target/i386: pull computation of string update value out of loop	Paolo Bonzini	1	-28/+26
2025-01-23	target/i386: execute multiple REP/REPZ iterations without leaving TB	Paolo Bonzini	1	-6/+49
2025-01-23	target/i386: optimize CX handling in repeated string operations	Paolo Bonzini	1	-1/+14
2025-01-23	target/i386: do not use gen_op_jz_ecx for repeated string operations	Paolo Bonzini	1	-1/+2
2025-01-23	target/i386: make cc_op handling more explicit for repeated string instructions.	Paolo Bonzini	1	-3/+21
2025-01-23	target/i386: fix RF handling for string instructions	Paolo Bonzini	1	-1/+21
2025-01-23	target/i386: tcg: move gen_set/reset_* earlier in the file	Paolo Bonzini	1	-40/+40
2025-01-23	target/i386: reorganize ops emitted by do_gen_rep, drop repz_opt	Paolo Bonzini	1	-47/+13
2025-01-23	target/i386: unify choice between single and repeated string instructions	Paolo Bonzini	2	-37/+17
2025-01-23	target/i386: unify REP and REPZ/REPNZ generation	Paolo Bonzini	1	-19/+20
2025-01-23	target/i386: remove trailing 1 from gen_{j, cmov, set}cc1	Paolo Bonzini	2	-12/+12
2025-01-23	target/i386: inline gen_jcc into sole caller	Paolo Bonzini	2	-9/+4
2025-01-22	rust: pl011: fix repr(C) for PL011Class	Paolo Bonzini	1	-0/+1
2025-01-19	hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events	Philippe Mathieu-Daudé	2	-12/+7
2025-01-19	target/riscv: Support Supm and Sspm as part of Zjpm v1.0	Alexey Baturo	2	-0/+25
2025-01-19	hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache	Jason Chien	1	-52/+153
2025-01-19	target/riscv: Add Smdbltrp ISA extension enable switch	Clément Léger	2	-0/+12
2025-01-19	target/riscv: Implement Smdbltrp behavior	Clément Léger	1	-16/+41
2025-01-19	target/riscv: Implement Smdbltrp sret, mret and mnret behavior	Clément Léger	1	-0/+12
2025-01-19	target/riscv: Add Smdbltrp CSRs handling	Clément Léger	4	-0/+18
2025-01-19	target/riscv: Add Ssdbltrp ISA extension enable switch	Clément Léger	1	-0/+2
2025-01-19	target/riscv: Implement Ssdbltrp exception handling	Clément Léger	3	-6/+39
2025-01-19	target/riscv: Implement Ssdbltrp sret, mret and mnret behavior	Clément Léger	1	-1/+34
2025-01-19	target/riscv: Add Ssdbltrp CSRs handling	Clément Léger	5	-12/+84
2025-01-19	target/riscv: Fix henvcfg potentially containing stale bits	Clément Léger	1	-2/+8
2025-01-19	target/riscv: Add configuration for S[m\|s]csrind, Smcdeleg/Ssccfg	Atish Patra	1	-0/+4
2025-01-19	target/riscv: Add implied rule for counter delegation extensions	Atish Patra	1	-1/+11
2025-01-19	target/riscv: Invoke pmu init after feature enable	Atish Patra	1	-14/+14
2025-01-19	target/riscv: Add counter delegation/configuration support	Kaiwen Xue	1	-12/+292
2025-01-19	target/riscv: Add select value range check for counter delegation	Kaiwen Xue	1	-1/+35
2025-01-19	target/riscv: Add counter delegation definitions	Kaiwen Xue	3	-1/+9
2025-01-19	target/riscv: Add properties for counter delegation ISA extensions	Atish Patra	2	-0/+4
2025-01-19	target/riscv: Support generic CSR indirect access	Kaiwen Xue	2	-6/+166
2025-01-19	target/riscv: Enable S*stateen bits for AIA	Atish Patra	1	-1/+84
2025-01-19	target/riscv: Decouple AIA processing from xiselect and xireg	Kaiwen Xue	1	-26/+139
2025-01-19	target/riscv: Add properties for Indirect CSR Access extension	Kaiwen Xue	2	-0/+4
2025-01-19	hw/riscv/virt: Remove unnecessary use of &first_cpu	Philippe Mathieu-Daudé	1	-1/+1
2025-01-19	target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu	Philippe Mathieu-Daudé	3	-4/+6
2025-01-19	target/riscv: Add Zicfilp support for Smrnmi	Frank Chang	3	-1/+20
2025-01-19	target/riscv: Add Smrnmi cpu extension	Tommy Wu	2	-0/+11
2025-01-19	target/riscv: Add Smrnmi mnret instruction	Tommy Wu	4	-5/+64
2025-01-19	target/riscv: Handle Smrnmi interrupt and exception	Tommy Wu	6	-7/+152
2025-01-19	target/riscv: Add Smrnmi CSRs	Tommy Wu	4	-0/+105