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2025-01-15acpi/ghes: Remove a duplicated out of bounds checkMauro Carvalho Chehab1-3/+1
2025-01-15acpi/ghes: Fix acpi_ghes_record_errors() argumentMauro Carvalho Chehab1-1/+1
2025-01-15acpi/ghes: better handle source_id and notificationMauro Carvalho Chehab1-14/+9
2025-01-15acpi/ghes: simplify the per-arch caller to build HEST tableMauro Carvalho Chehab3-7/+9
2025-01-15acpi/ghes: simplify acpi_ghes_record_errors() codeMauro Carvalho Chehab1-34/+36
2025-01-15acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVEDMauro Carvalho Chehab2-6/+4
2025-01-15pci/msix: Fix msix pba read vector poll end calculationNicholas Piggin1-1/+1
2025-01-15tests/qtest: Add intel-iommu testZhenzhong Duan4-0/+67
2025-01-15intel_iommu: Introduce a property to control FS1GP cap bit settingZhenzhong Duan2-1/+5
2025-01-15intel_iommu: Introduce a property x-flts for stage-1 translationZhenzhong Duan2-9/+21
2025-01-15tests/acpi: q35: Update host address width in DMARZhenzhong Duan2-1/+0
2025-01-15intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2Zhenzhong Duan2-1/+2
2025-01-15tests/acpi: q35: allow DMAR acpi table changesZhenzhong Duan1-0/+1
2025-01-15intel_iommu: piotlb invalidation should notify unmapZhenzhong Duan1-9/+34
2025-01-15intel_iommu: Add support for PASID-based device IOTLB invalidationClément Mathieu--Drif2-0/+61
2025-01-15intel_iommu: Add an internal API to find an address space with PASIDClément Mathieu--Drif1-15/+23
2025-01-15intel_iommu: Process PASID-based iotlb invalidationZhenzhong Duan2-0/+46
2025-01-15intel_iommu: Flush stage-1 cache in iotlb invalidationZhenzhong Duan2-6/+22
2025-01-15intel_iommu: Set accessed and dirty bits during stage-1 translationClément Mathieu--Drif2-1/+27
2025-01-15intel_iommu: Check stage-1 translation result with interrupt rangeZhenzhong Duan1-23/+25
2025-01-15intel_iommu: Check if the input address is canonicalClément Mathieu--Drif2-0/+24
2025-01-15intel_iommu: Implement stage-1 translationYi Liu2-4/+188
2025-01-15intel_iommu: Rename slpte to pteYi Liu3-77/+78
2025-0