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2025-01-15acpi/ghes: Remove a duplicated out of bounds checkMauro Carvalho Chehab1-3/+1
acpi_ghes_record_errors() has an assert() at the beginning to ensure that source_id will be lower than ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <df33b004d85b7b9aa388fb2ac530dcdea94b7edc.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: Fix acpi_ghes_record_errors() argumentMauro Carvalho Chehab1-1/+1
Align the header file with the actual implementation of this function, as the first argument is source ID and not notification type. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <d55f2a6ede5a168e42a20a228b2c066cb4c60939.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: better handle source_id and notificationMauro Carvalho Chehab1-14/+9
GHES has two fields that are stored on HEST error source blocks associated with notifications: - notification type, which is a number defined at the ACPI spec containing several arch-specific synchronous and assynchronous types; - source id, which is a HW/FW defined number, used to distinguish between different implemented sources. There could be several sources with the same notification type, which is dependent of the way each architecture maps notifications. Right now, build_ghes_v2() hardcodes a 1:1 mapping between such fields. Move it to two independent parameters, allowing the caller function to fill both. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <133ff72ea1041fed7dbcf97b7a2b0f4dfacde31a.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: simplify the per-arch caller to build HEST tableMauro Carvalho Chehab3-7/+9
The GHES driver requires not only a HEST table, but also a separate firmware file to store Error Structure records. It can't do one without the other. Simplify the caller logic for it to require one function. No functional changes. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <9584bb8953385e165681d5d185c503f8df8ef42f.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: simplify acpi_ghes_record_errors() codeMauro Carvalho Chehab1-34/+36
Reduce the ident of the function and prepares it for the next changes. No functional changes. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <19af4188535217213486d169e0501e592bc78a95.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVEDMauro Carvalho Chehab2-6/+4
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which has a better name. So, drop the duplication. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <9012bf4c9630adf15a22af3c88fda8270916887b.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15pci/msix: Fix msix pba read vector poll end calculationNicholas Piggin1-1/+1
The end vector calculation has a bug that results in polling fewer than required vectors when reading at a non-zero offset in PBA memory. Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20241212120402.1475053-1-npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15tests/qtest: Add intel-iommu testZhenzhong Duan4-0/+67
Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness when x-flts=on in scalable mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-21-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Introduce a property to control FS1GP cap bit settingZhenzhong Duan2-1/+5
This gives user flexibility to turn off FS1GP for debug purpose. It is also useful for future nesting feature. When host IOMMU doesn't support FS1GP but vIOMMU does, nested page table on host side works after turning FS1GP off in vIOMMU. This property has no effect when vIOMMU is in legacy mode or x-flts=off in scalable modme. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-20-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Introduce a property x-flts for stage-1 translationZhenzhong Duan2-9/+21
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. This vIOMMU implementation wants to simplify it with a new property "x-flts". When turned on in scalable mode, stage-1 translation is supported. When turned on in legacy mode, throw out error. With stage-1 translation support exposed to user, also accurate the pasid entry check in vtd_pe_type_check(). Suggested-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Message-Id: <20241212083757.605022-19-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15tests/acpi: q35: Update host address width in DMARZhenzhong Duan2-1/+0
Differences: @@ -1,39 +1,39 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024 + * Disassembly of /tmp/aml-SPJ4W2, Mon Nov 11 15:31:18 2024 * * ACPI Data Table [DMAR] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DMAR" [DMA Remapping table] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : 0C [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 -[024h 0036 1] Host Address Width : 26 +[024h 0036 1] Host Address Width : 2F [025h 0037 1] Flags : 01 [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00 [030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition] [032h 0050 2] Length : 0040 [034h 0052 1] Flags : 00 [035h 0053 1] Reserved : 00 [036h 0054 2] PCI Segment Number : 0000 [038h 0056 8] Register Base Address : 00000000FED90000 [040h 0064 1] Device Scope Type : 03 [IOAPIC Device] [041h 0065 1] Entry Length : 08 [042h 0066 2] Reserved : 0000 [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Message-Id: <20241212083757.605022-18-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2Zhenzhong Duan2-1/+2
According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 when stage-1 translation is turned on. For legacy and scalable modes, 48 is the default choice for modern OS when both 48 and 39 are supported. So it makes sense to set default to 48 for these two modes too starting from QEMU 9.2. Use pc_compat_9_1 to handle the compatibility for machines before 9.2. Suggested-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-17-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15tests/acpi: q35: allow DMAR acpi table changesZhenzhong Duan1-0/+1
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-16-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: piotlb invalidation should notify unmapZhenzhong Duan1-9/+34
This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. There is already a similar implementation in iotlb invalidation. So update vtd_iotlb_page_invalidate_notify() to make it work also for piotlb invalidation. For device that does not implement ATS capability or disable it but still caches the translation result, it is better to implement ATS cap or enable it if there is need to cache the translation result. Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Message-Id: <20241212083757.605022-15-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Add support for PASID-based device IOTLB invalidationClément Mathieu--Drif2-0/+61
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-14-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Add an internal API to find an address space with PASIDClément Mathieu--Drif1-15/+23
This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-13-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Process PASID-based iotlb invalidationZhenzhong Duan2-0/+46
PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-12-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Flush stage-1 cache in iotlb invalidationZhenzhong Duan2-6/+22
According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=001b) or nested (PGTT=011b) mapping associated with specified domain-id are invalidated. So per spec definition the Page-Selective-within-Domain Invalidation needs to flush first stage and nested cached IOTLB entries as well. We don't support nested yet and pass-through mapping is never cached, so what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-11-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Set accessed and dirty bits during stage-1 translationClément Mathieu--Drif2-1/+27
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-10-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Check stage-1 translation result with interrupt rangeZhenzhong Duan1-23/+25
Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation requests that result in an address in the interrupt range will be blocked with condition code LGN.4 or SGN.8." This applies to both stage-1 and stage-2 IOMMU page table, move the check from vtd_iova_to_slpte() to vtd_do_iommu_translate() so stage-1 page table could also be checked. By this chance, update the comment with correct section number. Suggested-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-9-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Check if the input address is canonicalClément Mathieu--Drif2-0/+24
Stage-1 translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-8-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Implement stage-1 translationYi Liu2-4/+188
This adds stage-1 page table walking to support stage-1 only translation in scalable mode. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-7-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Rename slpte to pteYi Liu3-77/+78
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation, rename variable and functions from slpte to pte whenever possible. But some are SST only, they are renamed with sl_ prefix. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-6-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb ↵Zhenzhong Duan2-6/+93
invalidation Per VT-d spec 4.1, 6.5.2.4, "Table 21. PASID-based-IOTLB Invalidation", PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With stage-1 translation introduced, guest could send PASID-selective PASID-based iotlb invalidation to flush either stage-1 or stage-2 entries. By this chance, remove old IOTLB related definitions which were unused. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-5-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Add a placeholder variable for scalable mode stage-1 translationZhenzhong Duan2-5/+19
Add an new element flts in IntelIOMMUState to mark stage-1 translation support in scalable mode, this element will be exposed as an intel_iommu property x-flts finally. For now, it's only a placehholder and used for address width compatibility check and block host device passthrough until nesting is supported. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Make pasid entry type check accurateZhenzhong Duan1-8/+4
When guest configures Nested Translation(011b) or First-stage Translation only (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation") Suggested-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-3-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Use the latest fault reasons defined by specYu Zhang2-10/+24
Spec revision 3.0 or above defines more detailed fault reasons for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Note spec revision has no relation with VERSION register, Guest kernel should not use that register to judge what features are supported. Instead cap/ecap bits should be checked. Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-2-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15tests: acpi: update expected blobsIgor Mammedov43-42/+0
previous patch has changed cpu hotplug AML, expected diff: @@ -2942,6 +2942,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) Name (CNEW, Package (0xFF) {}) + Name (CEJL, Package (0xFF) {}) Local3 = Zero Local4 = One While ((Local4 == One)) @@ -2949,6 +2950,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) Local4 = Zero Local0 = One Local1 = Zero + Local5 = Zero While (((Local0 == One) && (Local3 < One))) { Local0 = Zero @@ -2959,7 +2961,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) Break } - If ((Local1 == 0xFF)) + If (((Local1 == 0xFF) || (Local5 == 0xFF))) { Local4 = One Break @@ -2972,10 +2974,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) Local1++ Local0 = One } - ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + + If ((\_SB.PCI0.PRES.CRMV == One)) { - CTFY (Local3, 0x03) - \_SB.PCI0.PRES.CRMV = One + CEJL [Local5] = Local3 + Local5++ Local0 = One } @@ -2992,6 +2995,16 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) \_SB.PCI0.PRES.CINS = One Local2++ } + + Local2 = Zero + While ((Local2 < Local5)) + { + Local3 = DerefOf (CEJL [Local2]) + CTFY (Local3, 0x03) + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CRMV = One + Local2++ + } } Release (\_SB.PCI0.PRES.CPLK) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20241210163945.3422623-4-imammedo@redhat.com> Tested-by: Eric Mackay <eric.mackay@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15cpuhp: make sure that remove events are handled within the same SCIIgor Mammedov1-9/+34
CPU_SCAN_METHOD was processing insert events first and only if insert event was not present then it would check remove event. Normally it's not an issue as it doesn't make much sense tho hotplug and immediately unplug it. In this corner case, which can be reproduced with: qemu -smp 1,maxcpus=2 -cpu host -monitor stdio \ -drive if=pflash,format=raw,readonly,file=edk2-x86_64-code.fd * boot till GRUB prompt and pause guest (either via monitor or stop GRUB from automatic boot) * at monitor prompt add CPU: device_add host-x86_64-cpu,socket-id=0,core-id=1,thread-id=0,id=foo * let guest OS boot completely, and unplug CPU from monitor prompt: device_del foo which triggers GPE event that leads to CPU_SCAN_METHOD on guest side as result of above cpu 'foo' will not be hotunplugged, since QEMU sees insert event and ignores remove event (leaving it in pending state) for the GPE event. Any follow up CPU hotplug/unplug action from QEMU side will handle previously ignored event, so as workaround user can repeat device_del. Fix this corner-case by queuing remove events independently from insert events, aka the same way as we do with insert events. And then go over remove queue to send eject notify events to OSPM within the same GPE event. PS: Process remove queue after the cpu add queue has been processed 1st to ensure that OSPM gets hotadd evets after hotremove ones. PS2: Case where it's still borken happens when guest OS is Linux and device_del happens before guest OS initializes ACPI subsystem. Culprit in this case though is the guest kernel, which mangles GPE.sts (by clearing them up) and thus pending SCI turns to NOP leaving insert/remove events in pending state. That is the guest bug and should be fixed there. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reported-by: Eric Mackay <eric.mackay@oracle.com> Message-Id: <20241210163945.3422623-3-imammedo@redhat.com> Tested-by: Eric Mackay <eric.mackay@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15tests: acpi: whitelist expected blobsIgor Mammedov1-0/+42
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20241210163945.3422623-2-imammedo@redhat.com> Tested-by: Eric Mackay <eric.mackay@oracle.com> Acked-by: Ani Sinha <anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15pci: ensure valid link status bits for downstream portsSebastian Ott1-4/+8
PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport 0000:08:01.0: pciehp: Slot(2): Card present pcieport 0000:08:01.0: pciehp: Slot(2): Link Up pcieport 0000:08:01.0: pciehp: Slot(2): Cannot train link: status 0x2000 There's 2 cases where LNKSTA isn't setup properly: * the downstream device has no express capability * max link width of the bridge is 0 Move the sanity checks added via 88c869198aa63 ("pci: Sanity test minimum downstream LNKSTA") outside of the branch to make sure downstream ports always have a valid LNKSTA. Signed-off-by: Sebastian Ott <sebott@redhat.com> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-Id: <20241203121928.14861-1-sebott@redhat.com> Reviewed-by: Alex Williamson <ale