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2025-05-19target/riscv: Fix vslidedown with rvv_ta_all_1sAnton Blanchard1-2/+4
2025-05-19target/riscv: Fix the rvv reserved encoding of unmasked instructionsMax Chou1-9/+9
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store in...Max Chou1-2/+4
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instruct...Max Chou2-18/+68
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to vector integer extension ins...Max Chou1-1/+3
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OP...Max Chou1-1/+3
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) ...Max Chou1-0/+1
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check...Max Chou1-1/+2
2025-05-19target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to che...Max Chou1-0/+32
2025-05-19target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANSAnton Blanchard1-9/+9
2025-05-19target/riscv: rvv: Source vector registers cannot overlap mask registerAnton Blanchard1-3/+26
2025-05-19common-user/host/riscv: use tail pseudoinstruction for calling tailIcenowy Zheng1-2/+2
2025-05-19target/riscv: fix endless translation loop on big endian systemsZiqiao Kong1-2/+4
2025-05-19hw/riscv: Fix type conflict of GLib function pointersPaolo Bonzini1-2/+5
2025-05-19Expand the probe_pages helper function to handle probe flags.Paolo Savini1-20/+37
2025-05-19target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.Paolo Savini1-47/+108
2025-05-19hw/riscv: microchip_pfsoc: Rework documentationSebastian Huber1-81/+43
2025-05-19hw/riscv: Configurable MPFS CLINT timebase freqSebastian Huber2-4/+46
2025-05-19hw/riscv: Allow direct start of kernel for MPFSSebastian Huber1-17/+42
2025-05-19hw/riscv: Make FDT optional for MPFSSebastian Huber1-28/+28
2025-05-19hw/riscv: More flexible FDT placement for MPFSSebastian Huber1-2/+9
2025-05-19hw/misc: Add MPFS system reset supportSebastian Huber1-0/+7
2025-05-19Generate strided vector loads/stores with tcg nodes.Paolo Savini1-50/+273
2025-05-19target/riscv: pmp: remove redundant check in pmp_is_lockedLoïc Lefort1-5/+0
2025-05-19target/riscv: pmp: exit csr writes early if value was not changedLoïc Lefort1-7/+15
2025-05-19target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML modeLoïc Lefort1-36/+43
2025-05-19target/riscv: pmp: move Smepmp operation conversion into a functionLoïc Lefort1-10/+12
2025-05-19target/riscv: pmp: don't allow RLB to bypass rule privilegesLoïc Lefort1-20/+23
2025-05-19hw/riscv/virt-acpi-build: Add support for RIMTSunil V L1-0/+215
2025-05-19hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structureSunil V L2-0/+2
2025-05-15hw/nvme: fix nvme hotpluggingKlaus Jensen1-1/+0
2025-05-14mirror: Reduce I/O when destination is detect-zeroes:unmapEric Blake1-4/+9
2025-05-14tests: Add iotest mirror-sparse for recent patchesEric Blake2-0/+490
2025-05-14iotests/common.rc: add disk_usage functionAndrey Drobyshev2-5/+6
2025-05-14mirror: Skip writing zeroes when target is already zeroEric Blake1-14/+93
2025-05-14mirror: Skip pre-zeroing destination if it is already zeroEric Blake4-13/+33
2025-05-14mirror: Drop redundant zero_target parameterEric Blake4-26/+11
2025-05-14mirror: Allow QMP override to declare target already zeroEric Blake5-14/+44
2025-05-14mirror: Pass full sync mode rather than bool to internalsEric Blake1-12/+12
2025-05-14mirror: Minor refactoringEric Blake1-11/+11
2025-05-14iotests: Improve iotest 194 to mirror dataEric Blake1-0/+1
2025-05-14block: Add new bdrv_co_is_all_zeroes() functionEric Blake2-0/+64
2025-05-14block: Let bdrv_co_is_zero_fast consolidate adjacent extentsEric Blake1-12/+15
2025-05-14file-posix, gluster: Handle zero block status hint betterEric Blake2-2/+3
2025-05-14block: Expand block status mode from bool to flagsEric Blake25-86/+99
2025-05-14target/arm/tcg/vfp_helper: compile file twice (system, user)Pierrick Bouvier2-2/+5
2025-05-14target/arm/tcg/arith_helper: compile file oncePierrick Bouvier2-3/+4
2025-05-14target/arm/tcg/tlb-insns: compile file once (system)Pierrick Bouvier2-8/+1
2025-05-14target/arm/helper: restrict define_tlb_insn_regs to system targetPierrick Bouvier1-0/+2
2025-05-14target/arm/tcg/tlb_helper: compile file twice (system, user)Pierrick Bouvier2-2/+4