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2024-12-03hw/openrisc/openrisc_sim: keep serial@90000000 as defaultAhmad Fatoum1-6/+20
We used to only have a single UART on the platform and it was located at address 0x90000000. When the number of UARTs was increased to 4, the first UART remained at it's location, but instead of being the first one to be registered, it became the last. This caused QEMU to pick 0x90000300 as the default UART, which broke software that hardcoded the address of 0x90000000 and expected it's output to be visible when the user configured only a single console. This caused regressions[1] in the barebox test suite when updating to a newer QEMU. As there seems to be no good reason to register the UARTs in inverse order, let's register them by ascending address, so existing software can remain oblivious to the additional UART ports. Changing the order of uart registration alone breaks Linux which was choosing the UART at 0x90000300 as the default for ttyS0. To fix Linux we fix three things in the device tree: 1. Define stdout-path only one time for the first registered UART instead of incorrectly defining for each UART. 2. Change the UART alias name from 'uart0' to 'serial0' as almost all Linux tty drivers look for an alias starting with "serial". 3. Add the UART nodes so they appear in the final DTB in the order starting with the lowest address and working upwards. In summary these changes mean that the QEMU default UART (serial_hd(0)) is now setup where: * serial_hd(0) is the lowest-address UART * serial_hd(0) is listed first in the DTB * serial_hd(0) is the /chosen/stdout-path one * the /aliases/serial0 alias points at serial_hd(0) [1]: https://lore.barebox.org/barebox/707e7c50-aad1-4459-8796-0cc54bab32e2@pengutronix.de/T/#m5da26e8a799033301489a938b5d5667b81cef6ad Fixes: 777784bda468 ("hw/openrisc: support 4 serial ports in or1ksim") Cc: qemu-stable@nongnu.org Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> [stafford: Change to serial0 alias and update change message, reverse uart registration order] Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-13Update version for v9.2.0-rc0 releasePeter Maydell1-1/+1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-13edk2: update submodule to edk2-stable202408.01Gerd Hoffmann1-0/+0
Updates the subhook submodule to point to a edk2 mirror repo. Fixes recursive cloning of the edk2 submodule. Cc: Peter Maydell <peter.maydell@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2660 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20241111100701.2620020-1-kraxel@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-09hw/i386/pc: Don't try to init PCI NICs if there is no PCI busPeter Maydell1-1/+3
The 'isapc' machine type has no PCI bus, but pc_nic_init() still calls pci_init_nic_devices() passing it a NULL bus pointer. This causes the clang sanitizer to complain: $ ./build/clang/qemu-system-i386 -M isapc ../../hw/pci/pci.c:1866:39: runtime error: member access within null pointer of type 'PCIBus' (aka 'struct PCIBus') SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../../hw/pci/pci.c:1866:39 in This is because pci_init_nic_devices() does &bus->qbus which is undefined behaviour on a NULL pointer even though we're not actually dereferencing the pointer. (We don't actually crash as a result, so if you aren't running a sanitizer build then there are no user-visible effects.) Make pc_nic_init() avoid trying to initialize PCI NICs on a non-PCI system. Cc: qemu-stable@nongnu.org Fixes: 8d39f9ba14d64 ("hw/i386/pc: use qemu_get_nic_info() and pci_init_nic_devices()") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Link: https://lore.kernel.org/r/20241105171813.3031969-1-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09rust: qemu-api-macros: always process subprojects before dependenciesPaolo Bonzini1-0/+4
Avoid looking for Rust dependencies via cmake. Reviewed-by: Junjie Mao <junjie.mao@hotmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09i386/hvf: Removes duplicate/shadowed variables in hvf_vcpu_execPhil Dennis-Jordan1-3/+0
Pointers to the x86 CPU state already exist at the function scope, no need to re-obtain them in individual exit reason cases. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Link: https://lore.kernel.org/r/20241105155800.5461-6-phil@philjordan.eu Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09i386/hvf: Raise exception on error setting APICBASEPhil Dennis-Jordan1-2/+9
When setting the APICBASE MSR to an illegal value, the APIC implementation will return an error. This change forwards that report to the guest as an exception rather than ignoring it when using the hvf accelerator. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Link: https://lore.kernel.org/r/20241105155800.5461-5-phil@philjordan.eu Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09i386/hvf: Fixes startup memory leak (vmcs caps)Phil Dennis-Jordan1-1/+3
The hvf_caps data structure only exists once as part of the hvf accelerator state, but it is initialised during vCPU initialisation. This change therefore adds a check to ensure memory for it is only allocated once. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Link: https://lore.kernel.org/r/20241105155800.5461-4-phil@philjordan.eu Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09i386/hvf: Fix for UB in handling CPUID function 0xDPhil Dennis-Jordan1-2/+2
The handling for CPUID function 0xD (supported XSAVE features) was improved in a recent patch. Unfortunately, this appears to have introduced undefined behaviour for cases where ecx > 30, as the result of (1 << idx) is undefined if idx > 30. Per Intel SDM section 13.2, the behaviour for ecx values up to and including 62 are specified. This change therefore specifically sets all registers returned by the CPUID instruction to 0 for 63 and higher. Furthermore, the bit shift uses uint64_t, where behaviour for the entire range of 2..62 is safe and correct. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Link: https://lore.kernel.org/r/20241105155800.5461-3-phil@philjordan.eu Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09i386/hvf: Integrates x2APIC support with hvf accelPhil Dennis-Jordan2-1/+32
Support for x2APIC mode was recently introduced in the software emulated APIC implementation for TCG. Enabling it when using macOS’s hvf accelerator is useful and significantly helps performance, as Qemu currently uses the emulated APIC when running on hvf as well. This change wires up the read & write operations for the MSR VM exits and allow-lists the CPUID flag in the x86 hvf runtime. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Link: https://lore.kernel.org/r/20241105155800.5461-2-phil@philjordan.eu Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-09eif: cope with huge section sizesPaolo Bonzini1-7/+41
Check for overflow as well as allocation failure. Resolves Coverity CID 1564859. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-08ui/input-legacy.c: remove unused legacy qemu_add_kbd_event_handler() functionMark Cave-Ayland2-39/+0
Since the last keyboard device has now been converted over to use qemu_input_handler_register(), the legacy qemu_add_kbd_event_handler() function is now unused and can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241106120928.242443-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08next-kbd: convert to use qemu_input_handler_register()Mark Cave-Ayland1-55/+103
Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler() function to use qemu_input_handler_register(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20241106120928.242443-2-mark.cave-ayland@ilande.co.uk> [thuth: Removed the NEXTKBD_NO_KEY definition - replaced by 0 now] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-089pfs: fix crash on 'Treaddir' requestChristian Schoenebeck1-0/+5
A bad (broken or malicious) 9p client (guest) could cause QEMU host to crash by sending a 9p 'Treaddir' request with a numeric file ID (FID) that was previously opened for a file instead of an expected directory: #0 0x0000762aff8f4919 in __GI___rewinddir (dirp=0xf) at ../sysdeps/unix/sysv/linux/rewinddir.c:29 #1 0x0000557b7625fb40 in do_readdir_many (pdu=0x557bb67d2eb0, fidp=0x557bb67955b0, entries=0x762afe9fff58, offset=0, maxsize=131072, dostat=<optimized out>) at ../hw/9pfs/codir.c:101 #2 v9fs_co_readdir_many (pdu=pdu@entry=0x557bb67d2eb0, fidp=fidp@entry=0x557bb67955b0, entries=entries@entry=0x762afe9fff58, offset=0, maxsize=131072, dostat=false) at ../hw/9pfs/codir.c:226 #3 0x0000557b7625c1f9 in v9fs_do_readdir (pdu=0x557bb67d2eb0, fidp=0x557bb67955b0, offset=<optimized out>, max_count=<optimized out>) at ../hw/9pfs/9p.c:2488 #4 v9fs_readdir (opaque=0x557bb67d2eb0) at ../hw/9pfs/9p.c:2602 That's because V9fsFidOpenState was declared as union type. So the same memory region is used for either an open POSIX file handle (int), or a POSIX DIR* pointer, etc., so 9p server incorrectly used the previously opened (valid) POSIX file handle (0xf) as DIR* pointer, eventually causing a crash in glibc's rewinddir() function. Root cause was therefore a missing check in 9p server's 'Treaddir' request handler, which must ensure that the client supplied FID was really opened as directory stream before trying to access the aforementioned union and its DIR* member. Cc: qemu-stable@nongnu.org Fixes: d62dbb51f7 ("virtio-9p: Add fidtype so that we can do type ...") Reported-by: Akihiro Suda <suda.kyoto@gmail.com> Tested-by: Akihiro Suda <suda.kyoto@gmail.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <E1t8GnN-002RS8-E2@kylie.crudebyte.com>
2024-11-08hw/nvme: fix handling of over-committed queuesKlaus Jensen1-9/+12
If a host chooses to use the SQHD "hint" in the CQE to know if there is room in the submission queue for additional commands, it may result in a situation where there are not enough internal resources (struct NvmeRequest) available to process the command. For a lack of a better term, the host may "over-commit" the device (i.e., it may have more inflight commands than the queue size). For example, assume a queue with N entries. The host submits N commands and all are picked up for processing, advancing the head and emptying the queue. Regardless of which of these N commands complete first, the SQHD field of that CQE will indicate to the host that the queue is empty, which allows the host to issue N commands again. However, if the device has not posted CQEs for all the previous commands yet, the device will have less than N resources available to process the commands, so queue processing is suspended. And here lies an 11 year latent bug. In the absense of any additional tail updates on the submission queue, we never schedule the processing bottom-half again unless we observe a head update on an associated full completion queue. This has been sufficient to handle N-to-1 SQ/CQ setups (in the absense of over-commit of course). Incidentially, that "kick all associated SQs" mechanism can now be killed since we now just schedule queue processing when we return a processing resource to a non-empty submission queue, which happens to cover both edge cases. However, we must retain kicking the CQ if it was previously full. So, apparently, no previous driver tested with hw/nvme has ever used SQHD (e.g., neither the Linux NVMe driver or SPDK uses it). But then OSv shows up with the driver that actually does. I salute you. Fixes: f3c507adcd7b ("NVMe: Initial commit for new storage interface") Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2388 Reported-by: Waldemar Kozaczuk <jwkozaczuk@gmail.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2024-11-08tests: refresh package lists with latest libvirt-ciDaniel P. Berrangé13-37/+37
This updates the libvirt-ci submodule to pull in various fixes, the most notable reducing native package sets in cross builds. Some packages were mistakenly marked as native, rather than foreign, in libvirt-ci. Fixing this causes our dockerfiles to pick up the cross arch package instead of native one, thus improving our test coverage in a few areas. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20241106123525.511491-1-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08tests/functional: Split the test_aarch64_sbsaref testThomas Huth5-124/+172
The test_aarch64_sbsaref test is the test with the longest runtime in our functional test suite. Split it into parts so that it can be run on multiple CPUs in parallel. For this we have to move the fetch_firmware() function out of the class definition to be able to reuse it easily from the other tests (deriving the Aarch64SbsarefAlpine and Aarch64SbsarefFreeBSD directly from Aarch64SbsarefMachine does not work, unfortunately, since we'd inherit the test_sbsaref_edk2_firmware() function that way, causing it to be run multiple times - and keeping the fetch_firmware() in a separate class without the test_sbsaref_edk2_firmware() function also does not work since the "make precache-functional" won't work in that case ==> turning fetch_firmware() into a static function is the best option). Message-ID: <20241106175029.1000589-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08tests/functional: Bump timeouts of functional testsThomas Huth1-11/+13
When building QEMU with "--enable-debug" and running the tests in parallel with "make -j$(nproc) check-functional", many tests are still timing out due to our conservative timeout settings. Bump the timeouts of the problematic tests and also increase the default timeout to 90 seconds (from 60 seconds) to be on the safe side. Message-ID: <20241106170946.990731-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08tests/functional: Provide the user with hints where to find more log filesThomas Huth1-5/+13
Since the base.log and console.log files are not referenced from the meson test logs yet, they might be hard to find for the casual users. Thus let's print some hints in case a test case failed. For this we have to run unittest.main() with exit=False to get the results of the testing. Then we can iterate through the failed test cases to print out the information accordingly. Message-ID: <20241105123849.359391-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08tests/functional: Fix the ppc64_hv and the ppc_40p test for read-only assetsThomas Huth2-2/+4
Since commit 786bc2255256, cached asset files are read-only, so now we've got to use "read-only=true" in tests that try to use these files directly. Fixes: 786bc22552 ("tests/functional: make cached asset files read-only") Message-ID: <20241105160926.393852-1-thuth@redhat.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08test/functional: Fix Aspeed buildroot testsCédric Le Goater1-1/+1
Since commit 786bc2255256, cached asset files are read-only. Adjust the QEMU command line for buildroot tests to reflect the new constraint on the flash drive. Fixes: f04cb2d00d5c ("tests/functional: Convert most Aspeed machine tests") Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241105132339.2967202-1-clg@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08tests/functional: Convert the riscv_opensbi avocado test into a standalone testThomas Huth4-65/+47
The avocado test defined test functions for both, riscv32 and riscv64. Since we can run the whole file with multiple targets in the new framework, we can now consolidate the functions so we have to only define one function per machine now. Message-ID: <20240821082748.65853-23-thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08scripts/checkpatch.pl: Ignore ObjC #import lines for operator spacingPhil Dennis-Jordan1-1/+1
checkpatch.pl lints for spaces around operators including / (slash). Code lines starting with #include are ignored, as slashes in those represent path separators. In Objective-C code, #import is often used in preference to #include, as preprocessor-based multiple-#include defenses are considered non-idiomatic in that language. This change extends checkpatch.pl to treat #import lines in the same way as #include, avoiding false positives for "missing" spaces around path separators on those lines. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Message-ID: <20241024123555.25861-1-phil@philjordan.eu> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-07eif: cope with huge section offsetsPaolo Bonzini2-0/+8
Check for overflow to avoid that fseek() receives a sign-extended value. Cc: Dorjoy Chowdhury <dorjoychy111@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-07target/i386: Fix legacy page table walkAlexander Graf3-2/+3
Commit b56617bbcb4 ("target/i386: Walk NPT in guest real mode") added logic to run the page table walker even in real mode if we are in NPT mode. That function then determined whether real mode or paging is active based on whether the pg_mode variable was 0. Unfortunately pg_mode is 0 in two situations: 1) Paging is disabled (real mode) 2) Paging is in 2-level paging mode (32bit without PAE) That means the walker now assumed that 2-level paging mode was real mode, breaking NetBSD as well as Windows XP. To fix that, this patch adds a new PG flag to pg_mode which indicates whether paging is active at all and uses that to determine whether we are in real mode or not. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2654 Fixes: b56617bbcb4 ("target/i386: Walk NPT in guest real mode") Signed-off-by: Alexander Graf <graf@amazon.com> Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Link: https://lore.kernel.org/r/20241106154329.67218-1-graf@amazon.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-07rust: add meson_version to all subprojectsPaolo Bonzini11-0/+11
Otherwise, newer releases of meson complain. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-07target/i386/hvf: fix clang compilation warningPierrick Bouvier1-1/+1
../target/i386/hvf/x86_cpuid.c:35:28: error: a function declaration without a prototype is deprecated in all versions of C Fixes: 7cac7aa7040a823c585f1578a38f28e83c8bf3e1 Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Link: https://lore.kernel.org/r/20241104222102.1522688-1-pierrick.bouvier@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-07target/i386: add sha512, sm3, sm4 feature bitsPaolo Bonzini1-1/+1
SHA512, SM3, SM4 (CPUID[EAX=7,ECX=1).EAX bits 0 to 2) is supported by Clearwater Forest processor, add it to QEMU as it does not need any specific enablement. See https://lore.kernel.org/kvm/20241105054825.870939-1-tao1.su@linux.intel.com/ for reference. Reviewed-by: Tao Su <tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-07tests: Adjust path for swtpm state to use path under /var/tmp/Stefan Berger1-3/+6
To avoid AppArmor-related test failures when functional test are run from somewhere under /mnt, adjust the path to swtpm's state to use an AppArmor- supported path, such as /var/tmp, which is provided by the python function tempfile.TemporaryDirectory(). An update to swtpm's AppArmor profile is also being done to support /var/tmp. Link: https://lore.kernel.org/qemu-devel/CAFEAcA8A=kWLtTZ+nua-MpzqkaEjW5srOYZruZnE2tB6vmoMig@mail.gmail.com/ Link: https://github.com/stefanberger/swtpm/pull/944 Tested-by: Peter Maydell <peter.maydell@linaro.org> Fixes: f04cb2d00d5c ("tests/functional: Convert most Aspeed machine tests") Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2024-11-07qemu-ga: Avoiding freeing line prematurelyDehan Meng1-2/+1
It's now only freed at the end of the function. Signed-off-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Message-ID: <20241107102155.57573-4-kkostiuk@redhat.com> Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-11-07qemu-ga: Optimize var declaration and definitionDehan Meng1-50/+42
Variable declarations moved to the beginning of blocks Followed the coding style of using snake_case for variable names. Proper initialization of param 'size_t n' to '0' for Signed-off-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Message-ID: <20241107102155.57573-3-kkostiuk@redhat.com> Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-11-07qemu-ga: Add 'Null' check and Redefine 'route'Dehan Meng1-39/+44
sscanf return values are checked and add 'Null' check for mandatory parameters. And merged redundant route and networkroute variables. Signed-off-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Message-ID: <20241107102155.57573-2-kkostiuk@redhat.com> Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-11-07tests/functional: Convert the RV32-on-RV64 riscv testThomas Huth2-16/+13
A straggler that has been added to the Avocado framework while the conversion to the functional framework was already in progress... Move it over now, too! Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20241105103519.341304-1-thuth@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv/kvm: Update kvm exts to Linux v6.11Quan Zhou1-0/+7
Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Message-ID: <ada40759a79c0728652ace59579aa843cb7bf53f.1727164986.git.zhouquan@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: Inline unit-stride ld/st and corresponding functions for ↵Max Chou1-7/+11
performance In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-8-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st ↵Max Chou1-14/+63
instructions The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-7-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: rvv: Provide a fast path using direct access to host ram for ↵Max Chou1-27/+71
unit-stride load-only-first load instructions The unmasked unit-stride fault-only-first load instructions are similar to the unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-6-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: rvv: Provide a fast path using direct access to host ram for ↵Max Chou1-59/+70
unit-stride whole register load/store The vector unit-stride whole register load/store instructions are similar to unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Because the vector whole register load/store instructions do not need to handle the tail agnostic, so remove the vstart early exit checking. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: rvv: Provide a fast path using direct access to host ram for ↵Max Chou1-139/+224
unmasked unit-stride load/store This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store implementation with following optimizations: * Get the page boundary * Probing pages/resolving host memory address at the beginning if possible * Provide new interface to direct access host memory * Switch to the original slow TLB access when cross page element/violate page permission/violate pmp/watchpoints in page The original element load/store interface is replaced by the new element load/store functions with _tlb & _host postfix that means doing the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-4-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_usMax Chou1-1/+4
Because the real vl (evl) of vext_ldst_us may be different (e.g. vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function should be replaced by checking evl in vext_ldst_us. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: Set vdata.vm field for vector load/store whole register ↵Max Chou1-0/+3
instructions The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() checkDaniel Henrique Barboza1-1/+1
'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the 'switch' right before it if 'mode' isn't 0, 8, 9 or 10. 'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32. Reported by Coverity via a "DEADCODE" ticket. Resolves: Coverity CID 1564781 Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104123839.533442-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07hw/riscv/riscv-iommu: change 'depth' to intDaniel Henrique Barboza1-1/+1
Coverity reports an unsigned overflow when doing: for (; depth-- > 0; ) { When depth = 0 inside riscv_iommu_ctx_fetch(). Building it with a recent GCC the code doesn't actually break with depth = 0, i.e. the comparison "0-- > 0" will exit the loop instead of proceeding, but 'depth' will retain the overflow value afterwards. This behavior can be compiler dependent, so change 'depth' to int to remove this potential ambiguity. Resolves: Coverity CID 1564783 Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104123839.533442-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07hw/char/sifive_uart: Fix broken UART on big endian hostsThomas Huth1-1/+2
Casting a "uint32_t *" to a "uint8_t *" to get to the lowest 8-bit part of the value does not work on big endian hosts. We've got to take the proper detour through an 8-bit variable. Fixes: 53c1557b23 ("hw/char: sifive_uart: Print uart characters async") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241104163504.305955-1-thuth@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-06dockerfiles: install bindgen from cargo on Ubuntu 22.04Paolo Bonzini5-4/+19
Because Ubuntu 22.04 has a very old version of bindgen, that does not have the important option --allowlist-file, it will not be able to use --enable-rust out of the box. Instead, install the latest version of bindgen-cli via "cargo install" in the container, following QEMU's own documentation. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-06rust: make rustfmt optionalPaolo Bonzini1-0/+11
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-06rust: allow older version of bindgenPaolo Bonzini2-4/+39
Cope with the old version that is provided in Debian 12. --size_t-is-usize is needed on bindgen <0.61.0, and it was removed in bindgen 0.65.0, so check for it in meson.build. --merge-extern-blocks was added in 0.61.0. --formatter rustfmt was added in 0.65.0 and is the default, so remove it. Apart from Debian 12 and Ubuntu 22.04, all other supported distros have version 0.66.x of bindgen or newer (or do not have bindgen at all). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-05hw/riscv/iommu: fix build error with clangPierrick Bouvier1-3/+20
Introduced in 0c54acb8243, "hw/riscv: add RISC-V IOMMU base emulation". ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64' 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext) | ^ D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note: previous definition is here 217 | _pext_u64(unsigned long long __X, unsigned long long __Y) | ^ After a conversation on the mailing list, it was decided to rename and add a comment for this function. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104222225.1523751-1-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macroBernhard Beschow1-68/+50
The naming of the TypeInfo array is inspired by hcd-ohci-sysbus. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-25-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/rtc/ds1338: Prefer DEFINE_TYPES() macroBernhard Beschow1-12/+8
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-24-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>