summary refs log tree commit diff stats
path: root/scripts/coverage/compare_gcov_json.py (unfollow)
Commit message (Expand)AuthorFilesLines
2025-07-08hw/cxl-host: Add an index field to CXLFixedMemoryWindowJonathan Cameron2-3/+7
2025-07-08MAX78000: Add AES to SOCJackson Donaldson2-3/+11
2025-07-08MAX78000: AES implementationJackson Donaldson7-0/+303
2025-07-08MAX78000: Add TRNG to SOCJackson Donaldson2-1/+11
2025-07-08MAX78000: TRNG ImplementationJackson Donaldson7-0/+186
2025-07-08MAX78000: Add GCR to SOCJackson Donaldson2-2/+18
2025-07-08MAX78000: GCR ImplementationJackson Donaldson5-0/+473
2025-07-08MAX78000: Add UART to SOCJackson Donaldson2-4/+27
2025-07-08MAX78000: UART ImplementationJackson Donaldson5-0/+368
2025-07-08MAX78000: Add ICC to SOCJackson Donaldson2-4/+22
2025-07-08MAX78000: ICC ImplementationJackson Donaldson5-0/+158
2025-07-08MAX78000: Add MAX78000FTHR MachineJackson Donaldson5-0/+269
2025-07-04linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1Richard Henderson1-0/+8
2025-07-04target/arm: Enable FEAT_SME2p1 on -cpu maxRichard Henderson2-2/+14
2025-07-04target/arm: Implement SME2 BFMOPA (non-widening)Peter Maydell4-0/+64
2025-07-04target/arm: Implement FMOPA (non-widening) for fp16Peter Maydell4-0/+63
2025-07-04target/arm: Support FPCR.AH in SME FMOPS, BFMOPSRichard Henderson4-33/+161
2025-07-04target/arm: Rename BFMOPA to BFMOPA_wPeter Maydell4-5/+5
2025-07-04target/arm: Rename FMOPA_h to FMOPA_w_hPeter Maydell4-6/+6
2025-07-04target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1Richard Henderson4-0/+210
2025-07-04target/arm: Implement MOVAZ for SME2p1Richard Henderson4-11/+137
2025-07-04target/arm: Implement LD1Q, ST1Q for SVE2p1Richard Henderson4-2/+62
2025-07-04target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1Richard Henderson4-31/+156
2025-07-04target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.hRichard Henderson2-38/+69
2025-07-04target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1Richard Henderson5-27/+183
2025-07-04target/arm: Split the ST_zpri and ST_zprr patternsRichard Henderson1-8/+18
2025-07-04target/arm: Implement SME2 counted predicate register load/storeRichard Henderson4-0/+662
2025-07-04target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1Richard Henderson4-0/+37
2025-07-04target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1Richard Henderson4-1/+63
2025-07-04target/arm: Implement PMOV for SME2p1/SVE2p1Richard Henderson5-0/+207
2025-07-04target/arm: Implement EXTQ for SME2p1/SVE2p1Richard Henderson2-0/+51
2025-07-04target/arm: Implement DUPQ for SME2p1/SVE2p1Richard Henderson2-0/+27
2025-07-04target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1Richard Henderson4-1/+54
2025-07-04target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1Richard Henderson2-0/+36
2025-07-04target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1Richard Henderson4-27/+148
2025-07-04target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1Richard Henderson4-0/+65
2025-07-04target/arm: Implement SME2 SELRichard Henderson4-0/+362
2025-07-04target/arm: Implement SVE2p1 PEXTRichard Henderson5-0/+146
2025-07-04target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1Richard Henderson4-0/+113
2025-07-04target/arm: Implement SVE2p1 PTRUE (predicate as counter)Richard Henderson2-0/+17
2025-07-04target/arm: Implement SVE2p1 WHILE (predicate as counter)Richard Henderson4-5/+84
2025-07-04target/arm: Implement SVE2p1 WHILE (predicate pair)Richard Henderson4-4/+61
2025-07-04target/arm: Enable PSEL for SVE2p1Richard Henderson1-1/+1
2025-07-04target/arm: Split trans_WHILE to lt and gtRichard Henderson2-15/+12
2025-07-04target/arm: Move scale by esz into helper_sve_while*Richard Henderson2-8/+7
2025-07-04target/arm: Split out do_whileg from helper_sve_whilegRichard Henderson1-19/+20
2025-07-04target/arm: Split out do_whilel from helper_sve_whilelRichard Henderson1-10/+16
2025-07-04target/arm: Expand do_zero inlineRichard Henderson1-17/+11
2025-07-04target/arm: Fold predtest_ones into helper_sve_brknsRichard Henderson1-20/+14
2025-07-04target/arm: Introduce pred_count_testRichard Henderson1-34/+45