summary refs log tree commit diff stats
path: root/scripts/coverage/compare_gcov_json.py (unfollow)
Commit message (Expand)AuthorFilesLines
2025-09-29hw/arm/aspeed_ast27x0-fc: Drop dead return checksJamin Lin1-29/+14
2025-09-29hw/arm/aspeed: Move aspeed_load_vbootrom to common SoC codeJamin Lin3-30/+30
2025-09-29hw/arm/aspeed: Move aspeed_install_boot_rom to common SoC codeJamin Lin3-20/+22
2025-09-29hw/arm/aspeed: Move write_boot_rom to common SoC codeJamin Lin3-31/+35
2025-09-29hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC codeJamin Lin2-22/+23
2025-09-29tests/functional/arm/test_aspeed_ast2600: Add PCIe and network testJamin Lin1-0/+21
2025-09-29hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700Jamin Lin2-0/+75
2025-09-29hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST...Jamin Lin1-0/+2
2025-09-29hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocksJamin Lin2-0/+161
2025-09-29hw/pci-host/aspeed: Add AST2700 PCIe PHYJamin Lin2-0/+40
2025-09-29hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)Jamin Lin2-0/+75
2025-09-29hw/arm/aspeed: Wire up PCIe devices in SoC modelJamin Lin1-0/+13
2025-09-29hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address spaceJamin Lin3-0/+145
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurableJamin Lin2-0/+61
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe Root Device supportJamin Lin2-0/+67
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridgeJamin Lin3-0/+484
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe PHY modelJamin Lin6-0/+211
2025-09-29hw/pci/pci_ids: Add PCI vendor ID for ASPEEDJamin Lin1-0/+2
2025-09-29tests/functional/arm: Add AST2600 boot test with generated OTP imageKane-Chen-AS1-0/+15
2025-09-29tests/functional/arm: Add AST1030 boot test with generated OTP imageKane-Chen-AS1-4/+20
2025-09-29tests/functional/arm: Add helper to generate OTP imagesKane-Chen-AS1-0/+8
2025-09-29hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evbJamin Lin2-3/+3
2025-09-29docs/system/arm/aspeed: Document OTP memory optionsKane-Chen-AS1-0/+31
2025-09-29hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registersKane-Chen-AS2-0/+42
2025-09-29hw/misc/aspeed_sbc: Add CAMP2 support for OTP data readsKane-Chen-AS1-0/+27
2025-09-29hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCsKane-Chen-AS3-1/+18
2025-09-29hw/nvram/aspeed_otp: Add OTP programming semantics and tracingKane-Chen-AS2-1/+84
2025-09-29hw/nvram/aspeed_otp: Add 'drive' property to support block backendKane-Chen-AS1-1/+14
2025-09-29hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCsKane-Chen-AS2-1/+3
2025-09-29hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBCKane-Chen-AS3-0/+121
2025-09-29hw/nvram/aspeed_otp: Add ASPEED OTP memory device modelKane-Chen-AS3-0/+136
2025-09-28target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear maskDenis Sergeev1-1/+1
2025-09-28target/ppc: Deprecate Power8E and Power8NVLAditya Gupta2-4/+13
2025-09-28target/ppc: Introduce macro for deprecating PowerPC CPUsAditya Gupta2-2/+17
2025-09-28target/ppc: Move remaining floating-point move instructions to decodetree.Chinmay Rath3-40/+32
2025-09-28target/ppc: Move floating-point move instructions to decodetree.Chinmay Rath3-63/+28
2025-09-28target/ppc: Move floating-point compare instructions to decodetree.Chinmay Rath5-38/+22
2025-09-28target/ppc: Move floating-point rounding and conversion instructions to decod...Chinmay Rath5-114/+98
2025-09-28ppc/xive2: Fix integer overflow warning in xive2_redistribute()Gautam Menghani1-14/+31
2025-09-28ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not providedHarsh Prateek Bora1-4/+7
2025-09-28hw/intc/xics: Add missing call to register vmstate_icp_serverFabian Vogt1-0/+2
2025-09-28tests/functional: Add test for IBM PPE42 instructionsGlenn Miles3-0/+81
2025-09-28hw/ppc: Add a test machine for the IBM PPE42 CPUGlenn Miles4-0/+114
2025-09-28hw/ppc: Support for an IBM PPE42 CPU decrementerGlenn Miles2-1/+7
2025-09-28target/ppc: Add IBM PPE42 special instructionsGlenn Miles3-10/+694
2025-09-28target/ppc: Support for IBM PPE42 MMUGlenn Miles1-0/+4
2025-09-28target/ppc: Add IBM PPE42 exception modelGlenn Miles3-1/+213
2025-09-28target/ppc: IBM PPE42 exception flags and regsGlenn Miles1-0/+27
2025-09-28target/ppc: Add IBM PPE42 family of processorsGlenn Miles4-56/+205
2025-09-28target/ppc: IBM PPE42 general regs and flagsGlenn Miles2-1/+52