summary refs log tree commit diff stats
path: root/scripts/coverage/compare_gcov_json.py (unfollow)
Commit message (Collapse)AuthorFilesLines
2024-02-06memory-device: reintroduce memory region size checkDavid Hildenbrand1-0/+14
We used to check that the memory region size is multiples of the overall requested address alignment for the device memory address. We removed that check, because there are cases (i.e., hv-balloon) where devices unconditionally request an address alignment that has a very large alignment (i.e., 32 GiB), but the actual memory device size might not be multiples of that alignment. However, this change: (a) allows for some practically impossible DIMM sizes, like "1GB+1 byte". (b) allows for DIMMs that partially cover hugetlb pages, previously reported in [1]. Both scenarios don't make any sense: we might even waste memory. So let's reintroduce that check, but only check that the memory region size is multiples of the memory region alignment (i.e., page size, huge page size), but not any additional memory device requirements communicated using md->get_min_alignment(). The following examples now fail again as expected: (a) 1M with 2M THP qemu-system-x86_64 -m 4g,maxmem=16g,slots=1 -S -nodefaults -nographic \ -object memory-backend-ram,id=mem1,size=1M \ -device pc-dimm,id=dimm1,memdev=mem1 -> backend memory size must be multiple of 0x200000 (b) 1G+1byte qemu-system-x86_64 -m 4g,maxmem=16g,slots=1 -S -nodefaults -nographic \ -object memory-backend-ram,id=mem1,size=1073741825B \ -device pc-dimm,id=dimm1,memdev=mem1 -> backend memory size must be multiple of 0x200000 (c) Unliagned hugetlb size (2M) qemu-system-x86_64 -m 4g,maxmem=16g,slots=1 -S -nodefaults -nographic \ -object memory-backend-file,id=mem1,mem-path=/dev/hugepages/tmp,size=511M \ -device pc-dimm,id=dimm1,memdev=mem1 backend memory size must be multiple of 0x200000 (d) Unliagned hugetlb size (1G) qemu-system-x86_64 -m 4g,maxmem=16g,slots=1 -S -nodefaults -nographic \ -object memory-backend-file,id=mem1,mem-path=/dev/hugepages1G/tmp,size=2047M \ -device pc-dimm,id=dimm1,memdev=mem1 -> backend memory size must be multiple of 0x40000000 Note that this fix depends on a hv-balloon change to communicate its additional alignment requirements using get_min_alignment() instead of through the memory region. [1] https://lkml.kernel.org/r/f77d641d500324525ac036fe1827b3070de75fc1.1701088320.git.mprivozn@redhat.com Message-ID: <20240117135554.787344-3-david@redhat.com> Reported-by: Zhenyu Zhang <zhenyzha@redhat.com> Reported-by: Michal Privoznik <mprivozn@redhat.com> Fixes: eb1b7c4bd413 ("memory-device: Drop size alignment check") Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Tested-by: Mario Casquero <mcasquer@redhat.com> Reviewed-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-02-04hv-balloon: use get_min_alignment() to express 32 GiB alignmentDavid Hildenbrand1-16/+21
Let's implement the get_min_alignment() callback for memory devices, and copy for the device memory region the alignment of the host memory region. This mimics what virtio-mem does, and allows for re-introducing proper alignment checks for the memory region size (where we don't care about additional device requirements) in memory device core. Message-ID: <20240117135554.787344-2-david@redhat.com> Reviewed-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-02-03qga/qapi-schema: Move command description right after command nameMarkus Armbruster1-9/+9
Documentation of commands guest-ssh-get-authorized-keys, guest-ssh-add-authorized-keys, and guest-ssh-remove-authorized-keys describes the command's purpose after its arguments. Everywhere else, we do it the other way round. Move it for consistency. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240129115008.674248-6-armbru@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-02-03qga: Move type description right after type nameMarkus Armbruster1-2/+2
Documentation of type BlockdevOptionsIscsi describes the type's purpose after its members. Everywhere else, we do it the other way round. Move it for consistency. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240129115008.674248-5-armbru@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-02-03qapi: Elide "Potential additional modes" from generated docsMarkus Armbruster1-5/+6
Documentation of BlockExportRemoveMode has Potential additional modes to be added in the future: hide: Just hide export from new clients, leave existing connections as is. Remove export after all clients are disconnected. soft: Hide export from new clients, answer with ESHUTDOWN for all further requests from existing clients. I think this is useful only for developers. Elide it from generated documentation by turning it into a TODO section. This effectively reverts my own commit b71fd73cc45 (Revert "qapi: BlockExportRemoveMode: move comments to TODO"). At the time, I was about to elide TODO sections from the generated manual, I wasn't sure about this one, and decided to avoid change. And now I've made up my mind. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240129115008.674248-4-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2024-02-03qapi: Drop redundant documentation of conditionalMarkus Armbruster1-2/+0
Documentation generated for dump-skeys contains This command is only supported on s390 architecture. and If ~~ "TARGET_S390X" The former became redundant in commit 901a34a400a (qapi: add 'If:' section to generated documentation) added the latter. Drop the former. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240129115008.674248-3-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2024-02-03qapi: Drop redundant documentation of inherited membersMarkus Armbruster2-4/+0
Documentation generated for SchemaInfo looks like The members of "SchemaInfoBuiltin" when "meta-type" is ""builtin"" The members of "SchemaInfoEnum" when "meta-type" is ""enum"" The members of "SchemaInfoArray" when "meta-type" is ""array"" The members of "SchemaInfoObject" when "meta-type" is ""object"" The members of "SchemaInfoAlternate" when "meta-type" is ""alternate"" The members of "SchemaInfoCommand" when "meta-type" is ""command"" The members of "SchemaInfoEvent" when "meta-type" is ""event"" Additional members depend on the value of "meta-type". The last line became redundant when commit 88f63467c57 (qapi2texi: Generate reference to base type members) added the lines preceding it. Drop it. BlockdevOptions has the same issue. Drop Remaining options are determined by the block driver. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240129115008.674248-2-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2024-02-03linux-user/aarch64: Add padding before __kernel_rt_sigreturnRichard Henderson3-0/+4
Without this padding, an unwind through the signal handler will pick up the unwind info for the preceding syscall. This fixes gcc's 30_threads/thread/native_handle/cancel.cc. Cc: qemu-stable@nongnu.org Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") Resolves: https://linaro.atlassian.net/browse/GNU-974 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240202034427.504686-1-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASKRichard Henderson1-7/+0
These macros are no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-23-richard.henderson@linaro.org>
2024-02-03target/sparc: Split fcc out of env->fsrRichard Henderson4-522/+198
Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove cpu_fsrRichard Henderson3-113/+114
Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>
2024-02-03target/sparc: Split cexc and ftt from env->fsrRichard Henderson4-38/+48
These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>
2024-02-03target/sparc: Merge check_ieee_exceptions with FPop helpersRichard Henderson3-129/+219
If an exception is to be raised, the destination fp register should be unmodified. The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[]. We can simplify the entire implementation by having each FPOp helper call check_ieee_exceptions. For the moment this requires that all FPop helpers write to the TCG global cpu_fsr, so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org>
2024-02-03target/sparc: Clear cexc and ftt in do_check_ieee_exceptionsRichard Henderson2-16/+2
Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org>
2024-02-03target/sparc: Split ver from env->fsrRichard Henderson3-16/+23
This field is read-only. It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org>
2024-02-03target/sparc: Introduce cpu_get_fsr, cpu_put_fsrRichard Henderson9-18/+80
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove qt0, qt1 temporariesRichard Henderson3-8/+0
These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FdmulqRichard Henderson3-16/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FdTOq, FxTOqRichard Henderson3-10/+11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FsTOq, FiTOqRichard Henderson3-10/+11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FCMPq, FCMPEqRichard Henderson3-52/+41
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FqTOd, FqTOxRichard Henderson3-9/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FqTOs, FqTOiRichard Henderson3-9/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVqRichard Henderson3-28/+26
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org>
2024-02-03target/sparc: Use i128 for FSQRTqRichard Henderson3-8/+32
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>
2024-02-03target/sparc: Inline FNEG, FABSRichard Henderson3-72/+30
These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>
2024-02-03target/sparc: Introduce gen_{load,store}_fpr_QRichard Henderson1-6/+19
Use them for trans_FMOVq. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-5-richard.henderson@linaro.org>
2024-02-03target/sparc: Remove gen_dest_fpr_FRichard Henderson1-11/+6
Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-4-richard.henderson@linaro.org>
2024-02-03target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILLRichard Henderson1-16/+15
Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org>
2024-02-03target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPYRichard Henderson1-19/+26
Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-2-richard.henderson@linaro.org>
2024-02-03tcg/loongarch64: Set vector registers call clobberedRichard Henderson1-1/+1
Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-stable@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org>
2024-02-03tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub testIlya Leoshkevich1-1/+1
The `if not probe_proc_self_mem` check never passes, because probe_proc_self_mem is a function object, which is a truthy value. Add parentheses in order to perform a function call. Fixes: dc84d50a7f9b ("tests/tcg: Add the PROT_NONE gdbstub test") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240131220245.235993-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson23-49/+65
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03include/exec: Implement cpu_mmu_index genericallyRichard Henderson31-133/+34
For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/xtensa: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/tricore: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/sparc: Populate CPUClass.mmu_indexRichard Henderson2-28/+35
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/sh4: Populate CPUClass.mmu_indexRichard Henderson2-10/+22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/s390x: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/s390x: Split out s390x_env_mmu_indexRichard Henderson2-17/+21
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/rx: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/riscv: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/riscv: Replace cpu_mmu_index with riscv_env_mmu_indexRichard Henderson3-8/+9
Use the target-specific function name in preference to the generic name. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_indexRichard Henderson2-3/+3
Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/ppc: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/ppc: Split out ppc_env_mmu_indexRichard Henderson4-9/+14
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/openrisc: Populate CPUClass.mmu_indexRichard Henderson2-8/+15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/nios2: Populate CPUClass.mmu_indexRichard Henderson2-6/+13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/mips: Populate CPUClass.mmu_indexRichard Henderson1-0/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03target/mips: Split out mips_env_mmu_indexRichard Henderson6-10/+15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>