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2025-10-03target/riscv: Fix endianness swap on compressed instructionsvhaudiquet1-3/+3
2025-10-03hw/riscv/riscv-iommu: Fixup PDT Nested WalkGuo Ren (Alibaba DAMO Academy)1-2/+141
2025-10-03target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and...Max Chou3-20/+66
2025-10-03target/riscv: rvv: Modify minimum VLEN according to enabled vector extensionsMax Chou1-2/+17
2025-10-03target/riscv: rvv: Replace checking V by checking Zve32xMax Chou5-5/+7
2025-10-03target/riscv: Fix ssamoswap error handlingJim Shu3-0/+62
2025-10-03target/riscv: Fix SSP CSR error handling in VU/VS modeJim Shu1-0/+2
2025-10-03target/riscv: Fix the mepc when sspopchk triggers the exceptionJim Shu1-0/+1
2025-10-03target/riscv: do not use translator_ldl in opcode_atVladimir Isaev1-1/+2
2025-10-03qemu/osdep: align memory allocations to 2M on RISC-VXuemei Liu1-1/+1
2025-10-03target/riscv: use riscv_csrr in riscv_csr_readstove1-1/+1
2025-10-03target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN regPhilippe Mathieu-Daudé1-1/+1
2025-10-03target/riscv: Save stimer and vstimer in CPU vmstateTANG Tiancheng1-0/+25
2025-10-03hw/intc: Save timers array in RISC-V mtimer VMStateTANG Tiancheng2-2/+8
2025-10-03migration: Add support for a variable-length array of UINT32 pointersTANG Tiancheng1-0/+10
2025-10-02hw/intc: Save time_delta in RISC-V mtimer VMStateTANG Tiancheng1-2/+3
2025-10-02hw/char: sifive_uart: Add newline to error messageFrank Chang1-1/+1
2025-10-02hw/char: sifive_uart: Remove outdated comment about Tx FIFOFrank Chang1-6/+0
2025-10-02hw/char: sifive_uart: Avoid pushing Tx FIFO when size is zeroFrank Chang1-1/+3
2025-10-02hw/char: sifive_uart: Raise IRQ according to the Tx/Rx watermark thresholdsFrank Chang1-12/+12
2025-10-02roms/opensbi: Update to v1.7Daniel Henrique Barboza3-0/+0
2025-10-02target/riscv: implement MonitorDef HMP APIDaniel Henrique Barboza2-0/+149
2025-10-02linux-user/syscall.c: sync RISC-V hwprobe with LinuxDaniel Henrique Barboza1-0/+89
2025-10-02docs/interop/firmware: Add riscv64 to FirmwareArchitectureAndrea Bolognani1-1/+3
2025-10-02hw/riscv/riscv-iommu: Fix MSI table size limitAndrew Jones1-4/+7
2025-10-01migration-test: strv parameterSteve Sistare2-0/+18
2025-10-01migration-test: migrate_argsSteve Sistare2-24/+43
2025-10-01migration-test: misc exportsSteve Sistare4-0/+12
2025-10-01migration-test: shm path accessorSteve Sistare1-1/+6
2025-10-01migration-test: only_source optionSteve Sistare2-9/+17
2025-10-01tests/qtest: qtest_init_after_execSteve Sistare2-0/+27
2025-10-01tests/qtest: qtest_qemu_spawn_funcSteve Sistare1-5/+13
2025-10-01tests/qtest: qtest_create_test_stateSteve Sistare1-7/+14
2025-10-01tests/qtest: qtest_qemu_argsSteve Sistare2-23/+39
2025-10-01tests/qtest: export qtest_qemu_binarySteve Sistare2-1/+10
2025-10-01tests/qtest: optimize qtest_get_machinesSteve Sistare1-5/+7
2025-10-01tests/qtest/migration: Fix cpr-tests in case the machine is not availableThomas Huth3-4/+9
2025-10-01tests/qtest: Add missing checks for the availability of machinesThomas Huth3-3/+5
2025-10-01tracetool/syslog: add Rust supportTanish Desai6-2/+57
2025-10-01tracetool/ftrace: add Rust supportTanish Desai3-2/+48
2025-10-01tracetool/log: add Rust supportTanish Desai3-2/+54
2025-10-01log: change qemu_loglevel to unsignedPaolo Bonzini4-26/+26
2025-10-01tracetool/simple: add Rust supportTanish Desai3-0/+49
2025-10-01rust: pl011: add tracepointsPaolo Bonzini5-24/+50
2025-10-01rust: qdev: add minimal clock bindingsPaolo Bonzini1-0/+33
2025-10-01rust: add trace crateTanish Desai7-2/+83
2025-10-01tracetool: Add Rust format supportTanish Desai2-0/+219
2025-10-01tracetool/backend: remove redundant trace event checksTanish Desai5-28/+20
2025-10-01tracetool: add CHECK_TRACE_EVENT_GET_STATETanish Desai2-16/+36
2025-10-01trace/ftrace: move snprintf+write from tracepoints to ftrace.cPaolo Bonzini4-32/+24