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2025-09-29hw/arm/aspeed: Move write_boot_rom to common SoC codeJamin Lin3-31/+35
2025-09-29hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC codeJamin Lin2-22/+23
2025-09-29tests/functional/arm/test_aspeed_ast2600: Add PCIe and network testJamin Lin1-0/+21
2025-09-29hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700Jamin Lin2-0/+75
2025-09-29hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST...Jamin Lin1-0/+2
2025-09-29hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocksJamin Lin2-0/+161
2025-09-29hw/pci-host/aspeed: Add AST2700 PCIe PHYJamin Lin2-0/+40
2025-09-29hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)Jamin Lin2-0/+75
2025-09-29hw/arm/aspeed: Wire up PCIe devices in SoC modelJamin Lin1-0/+13
2025-09-29hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address spaceJamin Lin3-0/+145
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurableJamin Lin2-0/+61
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe Root Device supportJamin Lin2-0/+67
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridgeJamin Lin3-0/+484
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe PHY modelJamin Lin6-0/+211
2025-09-29hw/pci/pci_ids: Add PCI vendor ID for ASPEEDJamin Lin1-0/+2
2025-09-29tests/functional/arm: Add AST2600 boot test with generated OTP imageKane-Chen-AS1-0/+15
2025-09-29tests/functional/arm: Add AST1030 boot test with generated OTP imageKane-Chen-AS1-4/+20
2025-09-29tests/functional/arm: Add helper to generate OTP imagesKane-Chen-AS1-0/+8
2025-09-29hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evbJamin Lin2-3/+3
2025-09-29docs/system/arm/aspeed: Document OTP memory optionsKane-Chen-AS1-0/+31
2025-09-29hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registersKane-Chen-AS2-0/+42
2025-09-29hw/misc/aspeed_sbc: Add CAMP2 support for OTP data readsKane-Chen-AS1-0/+27
2025-09-29hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCsKane-Chen-AS3-1/+18
2025-09-29hw/nvram/aspeed_otp: Add OTP programming semantics and tracingKane-Chen-AS2-1/+84
2025-09-29hw/nvram/aspeed_otp: Add 'drive' property to support block backendKane-Chen-AS1-1/+14
2025-09-29hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCsKane-Chen-AS2-1/+3
2025-09-29hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBCKane-Chen-AS3-0/+121
2025-09-29hw/nvram/aspeed_otp: Add ASPEED OTP memory device modelKane-Chen-AS3-0/+136
2025-09-28hw/loongarch: Implement DINTC plug/unplug interfacesSong Gao2-0/+82
2025-09-28target/loongarch:Implement csrrd CSR_MSGIR registerSong Gao4-0/+28
2025-09-28target/loongarch: Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for msg interrupts.Song Gao1-2/+4
2025-09-28hw/loongarch: Implement dintc set irqSong Gao1-2/+30
2025-09-28hw/loongarch: Implement dintc realize and unrealizeSong Gao2-2/+24
2025-09-28hw/loongarch: DINTC add a MemoryRegionSong Gao5-1/+65
2025-09-28target/loongarch: add msg interrupt CSR registersSong Gao3-2/+37
2025-09-28loongarch: add a direct interrupt controller deviceSong Gao5-0/+108
2025-09-28hw/loongarch: add misc register support dmsiSong Gao1-0/+11
2025-09-28hw/loongarch: add virt feature dmsi supportSong Gao4-0/+94
2025-09-28target/loongarch: move some machine define to virt.hSong Gao2-21/+19
2025-09-28target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()Bibo Mao1-2/+1
2025-09-28target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()Bibo Mao1-2/+1
2025-09-28target/loongarch: Invalid tlb entry in invalidate_tlb()Bibo Mao1-1/+1
2025-09-28target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asidBibo Mao1-23/+13
2025-09-28target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_gBibo Mao1-23/+8
2025-09-28target/loongarch: Change return value type with loongarch_tlb_search_cb()Bibo Mao1-8/+14
2025-09-28target/loongarch: Add common API loongarch_tlb_search_cb()Bibo Mao1-6/+14
2025-09-28target/loongarch: Add tlb search callback in loongarch_tlb_search()Bibo Mao1-5/+15
2025-09-28target/loongarch: Fix page size set issue with CSR_STLBPSBibo Mao2-2/+4
2025-09-28target/loongarch: Update TLB index selection methodBibo Mao1-7/+42
2025-09-28target/loongarch: Reduce TLB flush with helper_tlbwrBibo Mao1-5/+24