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2024-01-10target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza3-1/+15
2024-01-10target/riscv: add satp_mode profile supportDaniel Henrique Barboza3-0/+42
2024-01-10target/riscv/cpu.c: add riscv_cpu_is_32bit()Daniel Henrique Barboza2-1/+7
2024-01-10target/riscv/cpu.c: finalize satp_mode earlierDaniel Henrique Barboza1-8/+8
2024-01-10target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza3-0/+34
2024-01-10target/riscv: implement svadeDaniel Henrique Barboza3-0/+7
2024-01-10target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza3-0/+27
2024-01-10riscv-qmp-cmds.c: add profile flags in cpu-model-expansionDaniel Henrique Barboza1-0/+14
2024-01-10target/riscv/tcg: validate profiles during finalizeDaniel Henrique Barboza1-0/+69
2024-01-10target/riscv/tcg: honor user choice for G MISA bitsDaniel Henrique Barboza1-25/+48
2024-01-10target/riscv/tcg: add hash table insert helpersDaniel Henrique Barboza1-12/+16
2024-01-10target/riscv/tcg: handle profile MISA bitsDaniel Henrique Barboza1-0/+21
2024-01-10target/riscv/tcg: add riscv_cpu_write_misa_bit()Daniel Henrique Barboza1-14/+18
2024-01-10target/riscv/tcg: add MISA user options hashDaniel Henrique Barboza1-1/+14
2024-01-10target/riscv/tcg: add user flag for profile supportDaniel Henrique Barboza1-0/+80
2024-01-10target/riscv/kvm: add 'rva22u64' flag as unavailableDaniel Henrique Barboza1-1/+6
2024-01-10target/riscv: add rva22u64 profile definitionDaniel Henrique Barboza2-0/+44
2024-01-10riscv-qmp-cmds.c: expose named features in cpu_model_expansionDaniel Henrique Barboza1-5/+25
2024-01-10target/riscv/tcg: add 'zic64b' supportDaniel Henrique Barboza4-0/+34
2024-01-10target/riscv: add zicbop extension flagDaniel Henrique Barboza3-0/+10
2024-01-10target/riscv: add rv64i CPUDaniel Henrique Barboza2-0/+48
2024-01-10target/riscv/tcg: update priv_ver on user_set extensionsDaniel Henrique Barboza1-0/+32
2024-01-10target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza1-4/+9
2024-01-10target/riscv: create TYPE_RISCV_VENDOR_CPUDaniel Henrique Barboza2-9/+22
2024-01-10docs/system/riscv: document acpi parameter of virt machineHeinrich Schuchardt1-0/+5
2024-01-10disas/riscv: Add amocas.[w,d,q] instructionsRob Bradford1-0/+9
2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li6-0/+165
2024-01-10hw/riscv/virt.c: fix the interrupts-extended property format of PLICYong-Xuan Wang1-20/+27
2024-01-10hw/riscv/virt-acpi-build.c: Add PLIC in MADTSunil V L1-0/+29
2024-01-10hw/riscv/virt-acpi-build.c: Add IO controllers and devicesSunil V L2-4/+76
2024-01-10hw/riscv/virt: Update GPEX MMIO related propertiesSunil V L2-15/+33
2024-01-10hw/pci-host/gpex: Define properties for MMIO rangesSunil V L3-8/+45
2024-01-10hw/riscv/virt-acpi-build.c: Add MMU node in RHCTSunil V L1-1/+35
2024-01-10hw/riscv/virt-acpi-build.c: Add CMO information in RHCTSunil V L1-8/+56
2024-01-10hw/riscv/virt-acpi-build.c: Add APLIC in the MADTSunil V L1-0/+34
2024-01-10hw/riscv/virt-acpi-build.c: Add IMSIC in the MADTSunil V L1-0/+35
2024-01-10hw/riscv/virt-acpi-build.c: Add AIA support in RINTCSunil V L1-4/+39
2024-01-10hw/riscv: virt: Make few IMSIC macros and functions publicSunil V L2-24/+26
2024-01-10hw/i386/acpi-microvm.c: Use common function to add virtio in DSDTSunil V L1-13/+2
2024-01-10hw/arm/virt-acpi-build.c: Migrate virtio creation to common locationSunil V L4-28/+54
2024-01-10hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common locationSunil V L5-34/+43
2024-01-10target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()Daniel Henrique Barboza1-19/+21
2024-01-10target/riscv/kvm: add RISCV_CONFIG_REG()Daniel Henrique Barboza1-14/+11
2024-01-10target/riscv/kvm: change timer regs size to u64Daniel Henrique Barboza1-13/+13
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64Daniel Henrique Barboza1-3/+8
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32Daniel Henrique Barboza1-3/+8
2024-01-10target/riscv/cpu.c: fix machine IDs gettersDaniel Henrique Barboza1-6/+6
2024-01-10target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov2-18/+16
2024-01-10target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei1-1/+4
2024-01-10target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei1-1/+1