summary refs log tree commit diff stats
path: root/scripts/coverage/compare_gcov_json.py (unfollow)
Commit message (Expand)AuthorFilesLines
2023-11-07tests/tcg/s390x: Test LAALG with negative cc_srcIlya Leoshkevich2-0/+28
2023-11-07target/s390x: Fix LAALG not updating cc_srcIlya Leoshkevich2-3/+18
2023-11-07tests/tcg/s390x: Test CLC with inaccessible second operandIlya Leoshkevich2-0/+49
2023-11-07target/s390x: Fix CLC corrupting cc_srcIlya Leoshkevich1-2/+5
2023-11-07target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block()Philippe Mathieu-Daudé1-5/+1
2023-11-07s390/sclp: fix SCLP facility mapHeiko Carstens1-3/+1
2023-11-07tests/avocado: Allow newer versions of tesseract in the nextcube testThomas Huth2-14/+5
2023-11-07MAINTAINERS: Add artist.c to the hppa machine sectionThomas Huth1-0/+1
2023-11-07MAINTAINERS: Add the virtio-gpu documentation to the corresponding sectionThomas Huth1-0/+1
2023-11-07docs/about/deprecated: Document RISC-V "pmu-num" deprecationRob Bradford1-0/+12
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford5-12/+51
2023-11-07target/riscv: Use existing PMU counter mask in FDT generationRob Bradford3-7/+3
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford1-2/+3
2023-11-07target/riscv: Propagate error from PMU setupRob Bradford3-12/+18
2023-11-07target/riscv: cpu: Set the OpenTitan priv to 1.12.0Alistair Francis1-1/+1
2023-11-07hw/ssi: ibex_spi_host: Clear the interrupt even if disabledAlistair Francis1-2/+4
2023-11-07disas/riscv: Replace TABs with spaceMax Chou1-3/+3
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou1-0/+137
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou2-1/+14
2023-11-07disas/riscv: Add rv_fmt_vd_vs2_uimm formatMax Chou1-0/+1
2023-11-07target/riscv: Move vector crypto extensions to riscv_cpu_extensionsMax Chou1-18/+18
2023-11-07target/riscv: Expose Zvks[c|g] extnesion propertiesMax Chou1-0/+6
2023-11-07target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou2-0/+20
2023-11-07target/riscv: Expose Zvkn[c|g] extnesion propertiesMax Chou1-0/+6
2023-11-07target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou2-0/+23
2023-11-07target/riscv: Expose Zvkb extension propertyMax Chou1-0/+2
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou1-13/+24
2023-11-07target/riscv: Add cfg property for Zvkb extensionMax Chou2-3/+4
2023-11-07target/riscv: Expose Zvkt extension propertyMax Chou1-0/+2
2023-11-07target/riscv: Add cfg property for Zvkt extensionMax Chou2-0/+6
2023-11-07MAINTAINERS: update mail address for Weiwei LiWeiwei Li1-1/+1
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt1-2/+5
2023-11-07target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapotDaniel Henrique Barboza1-0/+5
2023-11-07target/riscv/kvm: add zihpm regDaniel Henrique Barboza1-0/+1
2023-11-07target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza3-0/+17
2023-11-07target/riscv/kvm: add zicntr regDaniel Henrique Barboza1-0/+1
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza4-0/+25
2023-11-07target/riscv: pmp: Ignore writes when RW=01Mayuresh Chitale1-0/+5
2023-11-07target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale3-0/+23
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan5-17/+15
2023-11-07target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansionDaniel Henrique Barboza1-0/+20
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza4-1/+17
2023-11-07target/riscv: handle custom props in qmp_query_cpu_model_expansionDaniel Henrique Barboza1-0/+65
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza4-30/+53
2023-11-07qapi,risc-v: add query-cpu-model-expansionDaniel Henrique Barboza2-2/+79
2023-11-07target/riscv/kvm/kvm-cpu.c: add missing property getters()Daniel Henrique Barboza1-3/+37
2023-11-07docs/system/riscv: update 'virt' machine core limitDaniel Henrique Barboza1-1/+1
2023-11-07linux-user/riscv: change default cpu to 'max'Daniel Henrique Barboza1-2/+1
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal5-32/+236
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal6-38/+291