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2021-07-13target/openrisc: Use tcg_constant_*Richard Henderson1-33/+9
Replace uses of tcg_const_* allocate and free close together with tcg_constant_*. Reviewed-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/alpha: Use tcg_constant_* elsewhereRichard Henderson1-32/+14
Replace the remaining uses of tcg_const_*. These uses are all local, with the allocate and free close together. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/alpha: Use tcg_constant_i64 for zero and litRichard Henderson1-14/+2
These constant temps do not need to be freed, and therefore need less bookkeeping from tcg producers. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/alpha: Use dest_sink for HW_RET temporaryRichard Henderson1-1/+1
This temp is automatically freed, just like ctx->lit. But we're about to remove ctx->lit, so use sink instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/alpha: Store set into rx flagRichard Henderson1-5/+1
A paste-o meant that we wrote back the existing value of the RX flag rather than changing it to TMP. Use tcg_constant_i64 while we're at it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/i386: Correct implementation for FCS, FIP, FDS and FDPZiqiao Kong3-9/+56
Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8. Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not implemented by design in this patch and will be added along with TCG features flag in a separate patch later. Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20210530150112.74411-2-ziqiaokong@gmail.com> [rth: Push FDS/FDP handling down into mod != 3 case; free last_addr.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/i386: Split out do_fninitRichard Henderson1-14/+8
Do not call helper_fninit directly from helper_xrstor. Do call the new helper from do_fsave. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/i386: Trivial code motion and code style fixZiqiao Kong1-435/+446
A new pair of braces has to be added to declare variables in the case block. The code style is also fixed according to the transalte.c itself during the code motion. Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/i386: Tidy hw_breakpoint_removeDmitry Voronetskiy1-2/+2
Since cpu_breakpoint and cpu_watchpoint are in a union, the code should access only one of them. Signed-off-by: Dmitry Voronetskiy <davoronetskiy@gmail.com> Message-Id: <20210613180838.21349-1-davoronetskiy@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-12trace, lttng: require .pc filesPaolo Bonzini3-21/+3
The next version of lttng-libs will not require liburcu at run time anymore. Therefore, it is expected that distros will not include the urcubp libraries anymore when installing lttng-ust-devel. To avoid future problems, just require pkg-config to detect lttng-ust. The .pc files for lttng-ust correctly include liburcubp.a for static builds, and have always done since pkg-config files were added in 2011. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20210712155710.520889-1-pbonzini@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-07-12trace/simple: add st_init_groupGerd Hoffmann3-0/+17
Add helper function and call it for each trace event group added. Makes sure that events added at module load time are initialized properly. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20210601132414.432430-6-kraxel@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-07-12trace/simple: pass iter to st_write_event_mappingGerd Hoffmann1-5/+5
Pass an iter to st_write_event_mapping, so the function can interate different things depending on how we initialize the iter. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20210601132414.432430-5-kraxel@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-07-12trace: add trace_event_iter_init_groupGerd Hoffmann2-3/+29
This allows to interate over an event group. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20210601132414.432430-4-kraxel@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-07-12trace: iter init tweaksGerd Hoffmann6-16/+31
Rename trace_event_iter_init() to trace_event_iter_init_pattern(), add trace_event_iter_init_all() for interating over all events. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20210601132414.432430-3-kraxel@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-07-12qemu-trace-stap: changing SYSTEMTAP_TAPSET considered harmful.Gerd Hoffmann1-10/+4
Setting SYSTEMTAP_TAPSET to some value other than /usr/share/systemtap/tapsets results in systemtap not finding the standard tapset library any more, which in turn breaks tracing because pid() and other standard systemtap functions are not available any more. So using SYSTEMTAP_TAPSET to point systemtap to the qemu probes will only work for the prefix=/usr installs because both qemu and system tapsets in the same directory then. All other prefixes are broken. Fix that by using the "-I $tapsetdir" command line switch instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20210601132414.432430-2-kraxel@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-07-12nbd: register yank function earlierLukas Straub1-3/+5
Although unlikely, qemu might hang in nbd_send_request(). Allow recovery in this case by registering the yank function before calling it. Signed-off-by: Lukas Straub <lukasstraub2@web.de> Message-Id: <20210704000730.1befb596@gecko.fritz.box> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Eric Blake <eblake@redhat.com>
2021-07-12qemu-img: Reword 'qemu-img map --output=json' docsEric Blake1-10/+10
Reword the paragraphs to list the JSON key first, rather than in the middle of prose. Suggested-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20210707184125.2551140-1-eblake@redhat.com> Reviewed-by: Nir Soffer <nsoffer@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
2021-07-12qemu-img: Make unallocated part of backing chain obvious in mapEric Blake18-690/+749
The recently-added NBD context qemu:allocation-depth is able to distinguish between locally-present data (even when that data is sparse) [shown as depth 1 over NBD], and data that could not be found anywhere in the backing chain [shown as depth 0]; and the libnbd project was recently patched to give the human-readable name "absent" to an allocation-depth of 0. But qemu-img map --output=json predates that addition, and has the unfortunate behavior that all portions of the backing chain that resolve without finding a hit in any backing layer report the same depth as the final backing layer. This makes it harder to reconstruct a qcow2 backing chain using just 'qemu-img map' output, especially when using "backing":null to artificially limit a backing chain, because it is impossible to distinguish between a QCOW2_CLUSTER_UNALLOCATED (which defers to a [missing] backing file) and a QCOW2_CLUSTER_ZERO_PLAIN cluster (which would override any backing file), since both types of clusters otherwise show as "data":false,"zero":true" (but note that we can distinguish a QCOW2_CLUSTER_ZERO_ALLOCATED, which would also have an "offset": listing). The task of reconstructing a qcow2 chain was made harder in commit 0da9856851 (nbd: server: Report holes for raw images), because prior to that point, it was possible to abuse NBD's block status command to see which portions of a qcow2 file resulted in BDRV_BLOCK_ALLOCATED (showing up as NBD_STATE_ZERO in isolation) vs. missing from the chain (showing up as NBD_STATE_ZERO|NBD_STATE_HOLE); but now qemu reports more accurate sparseness information over NBD. An obvious solution is to make 'qemu-img map --output=json' add an additional "present":false designation to any cluster lacking an allocation anywhere in the chain, without any change to the "depth" parameter to avoid breaking existing clients. The iotests have several examples where this distinction demonstrates the additional accuracy. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20210701190655.2131223-3-eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> [eblake: fix more iotest fallout] Signed-off-by: Eric Blake <eblake@redhat.com>
2021-07-12iotests: Improve and rename test 309 to nbd-qemu-allocationEric Blake2-2/+15
Enhance the test to inspect what qemu-nbd is advertising during handshake, and rename it now that we support useful iotest names. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20210701190655.2131223-2-eblake@redhat.com>
2021-07-12hw/sd/sdcard: Check for valid address range in SEND_WRITE_PROT (CMD30)Philippe Mathieu-Daudé4-1/+74
OSS-Fuzz found sending illegal addresses when querying the write protection bits triggers an assertion: qemu-fuzz-i386: hw/sd/sd.c:824: uint32_t sd_wpbits(SDState *, uint64_t): Assertion `wpnum < sd->wpgrps_size' failed. ==11578== ERROR: libFuzzer: deadly signal #8 0x7ffff628e091 in __assert_fail #9 0x5555588f1a3c in sd_wpbits hw/sd/sd.c:824:9 #10 0x5555588dd271 in sd_normal_command hw/sd/sd.c:1383:38 #11 0x5555588d777c in sd_do_command hw/sd/sd.c #12 0x555558cb25a0 in sdbus_do_command hw/sd/core.c:100:16 #13 0x555558e02a9a in sdhci_send_command hw/sd/sdhci.c:337:12 #14 0x555558dffa46 in sdhci_write hw/sd/sdhci.c:1187:9 #15 0x5555598b9d76 in memory_region_write_accessor softmmu/memory.c:489:5 Similarly to commit 8573378e62d ("hw/sd: fix out-of-bounds check for multi block reads"), check the address range before sending the status of the write protection bits. Include the qtest reproducer provided by Alexander Bulekov: $ make check-qtest-i386 ... Running test qtest-i386/fuzz-sdcard-test qemu-system-i386: ../hw/sd/sd.c:824: sd_wpbits: Assertion `wpnum < sd->wpgrps_size' failed. Reported-by: OSS-Fuzz (Issue 29225) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/450 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20210702155900.148665-4-f4bug@amsat.org>
2021-07-12hw/sd/sdcard: Extract address_in_range() helper, log invalid accessesPhilippe Mathieu-Daudé1-12/+21
Multiple commands have to check the address requested is valid. Extract this code pattern as a new address_in_range() helper, and log invalid accesses as guest errors. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210624142209.1193073-3-f4bug@amsat.org>
2021-07-12hw/sd/sdcard: When card is in wrong state, log which state it isPhilippe Mathieu-Daudé1-1/+2
We report the card is in an inconsistent state, but don't precise in which state it is. Add this information, as it is useful when debugging problems. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210624142209.1193073-2-f4bug@amsat.org> Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
2021-07-11dp8393x: don't force 32-bit register accessMark Cave-Ayland1-5/+9
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" set .impl.min_access_size and .impl.max_access_size to 4 to try and fix the Linux jazzsonic driver which uses 32-bit accesses. The problem with forcing the register access to 32-bit in this way is that since the dp8393x uses 16-bit registers, a manual endian swap is required for devices on big endian machines with 32-bit accesses. For both access sizes and machine endians the QEMU memory API can do the right thing automatically: all that is needed is to set .impl.min_access_size to 2 to declare that the dp8393x implements 16-bit registers. Normally .impl.max_access_size should also be set to 2, however that doesn't quite work in this case since the register stride is specified using a (dynamic) it_shift property which is applied during the MMIO access itself. The effect of this is that for a 32-bit access the memory API performs 2 x 16-bit accesses, but the use of it_shift within the MMIO access itself causes the register value to be repeated in both the top 16-bits and bottom 16-bits. The Linux jazzsonic driver expects the stride to be zero-extended up to access size and therefore fails to correctly detect the dp8393x device due to the extra data in the top 16-bits. The solution here is to remove .impl.max_access_size so that the memory API will correctly zero-extend the 16-bit registers to the access size up to and including it_shift. Since it_shift is never greater than 2 than this will always do the right thing for both 16-bit and 32-bit accesses regardless of the machine endian, allowing the manual endian swap code to be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: 3fe9a838ec ("dp8393x: Always use 32-bit accesses") Message-Id: <20210705214929.17222-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Finn Thain <fthain@linux-m68k.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-07-11dp8393x: Rewrite dp8393x_get() / dp8393x_put()Philippe Mathieu-Daudé1-97/+63
Instead of accessing N registers via a single address_space API call using a temporary buffer (stored in the device state) and updating each register, move the address_space call in the register put/get. The load/store and word size checks are moved to put/get too. This simplifies a bit, making the code easier to read. Co-developed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Message-Id: <20210710174954.2577195-8-f4bug@amsat.org>
2021-07-11dp8393x: Store CAM registers as 16-bitPhilippe Mathieu-Daudé1-15/+12
Per the DP83932C datasheet from July 1995: 4.0 SONIC Registers 4.1 THE CAM UNIT The Content Addressable Memory (CAM) consists of sixteen 48-bit entries for complete address filtering of network packets. Each entry corresponds to a 48-bit destination address that is user programmable and can contain any combination of Multicast or Physical addresses. Each entry is partitioned into three 16-bit CAM cells accessible through CAM Address Ports (CAP 2, CAP 1 and CAP 0) with CAP0 corresponding to the least significant 16 bits of the Destination Address and CAP2 corresponding to the most significant bits. Store the CAM registers as 16-bit as it simplifies the code. Having now the CAM registers as arrays of 3 uint16_t, we can avoid using the VMSTATE_BUFFER_UNSAFE macro by using VMSTATE_UINT16_2DARRAY which is more appropriate. This breaks the migration stream however. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Message-Id: <20210710174954.2577195-5-f4bug@amsat.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-07-11dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definitionPhilippe Mathieu-Daudé1-3/+4
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Message-Id: <20210710174954.2577195-3-f4bug@amsat.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-07-11dp8393x: Replace address_space_rw(is_write=1) by address_space_write()Philippe Mathieu-Daudé1-4/+4
Replace address_space_rw(is_write=1) by address_space_write() and remove pointless cast. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Message-Id: <20210710174954.2577195-2-f4bug@amsat.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-07-11dp8393x: fix CAM descriptor entry indexMark Cave-Ayland1-2/+2
Currently when a LOAD CAM command is executed the entries are loaded into the CAM from memory in order which is incorrect. According to the datasheet the first entry in the CAM descriptor is the entry index which means that each descriptor may update any single entry in the CAM rather than the Nth entry. Decode the CAM entry index and use it store the descriptor in the appropriate slot in the CAM. This fixes the issue where the MacOS toolbox loads a single CAM descriptor into the final slot in order to perform a loopback test which must succeed before the Ethernet port is enabled. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Finn Thain <fthain@linux-m68k.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210625065401.30170-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips: Rewrite UHI errno_mips() using switch statementPhilippe Mathieu-Daudé1-15/+9
Linking on Haiku OS fails: /boot/system/develop/tools/bin/../lib/gcc/x86_64-unknown-haiku/8.3.0/../../../../x86_64-unknown-haiku/bin/ld: error: libqemu-mips-softmmu.fa.p/target_mips_tcg_sysemu_mips-semi.c.o(.rodata) is too large (0xffff405a bytes) /boot/system/develop/tools/bin/../lib/gcc/x86_64-unknown-haiku/8.3.0/../../../../x86_64-unknown-haiku/bin/ld: final link failed: memory exhausted collect2: error: ld returned 1 exit status This is because the host_to_mips_errno[] uses errno as index, for example: static const uint16_t host_to_mips_errno[] = { [ENAMETOOLONG] = 91, ... and Haiku defines [*] ENAMETOOLONG as: 12 /* Error baselines */ 13 #define B_GENERAL_ERROR_BASE INT_MIN .. 22 #define B_STORAGE_ERROR_BASE (B_GENERAL_ERROR_BASE + 0x6000) ... 106 #define B_NAME_TOO_LONG (B_STORAGE_ERROR_BASE + 4) ... 211 #define ENAMETOOLONG B_TO_POSIX_ERROR(B_NAME_TOO_LONG) so the array ends up beeing indeed too big. Since POSIX errno can't be use as indexes on Haiku, rewrite errno_mips() using a switch statement. [*] https://github.com/haiku/haiku/blob/r1beta3/headers/os/support/Errors.h#L130 Reported-by: Richard Zak <richard.j.zak@gmail.com> Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210706130723.1178961-1-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce SQ opcode (Store Quadword)Philippe Mathieu-Daudé2-0/+28
Introduce the SQ opcode (Store Quadword). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-27-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce LQ opcode (Load Quadword)Philippe Mathieu-Daudé3-14/+45
Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)Philippe Mathieu-Daudé2-0/+29
Introduce the PROT3W opcode (Parallel Rotate 3 Words). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-25-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)Philippe Mathieu-Daudé2-0/+31
Introduce the PPACW opcode (Parallel Pack to Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-22-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)Philippe Mathieu-Daudé2-0/+21
Introduce the 'Parallel Compare for Greater Than' opcodes: - PCGTB (Parallel Compare for Greater Than Byte) - PCGTH (Parallel Compare for Greater Than Halfword) - PCGTW (Parallel Compare for Greater Than Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-15-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)Philippe Mathieu-Daudé2-0/+69
Introduce the 'Parallel Compare for Equal' opcodes: - PCEQB (Parallel Compare for Equal Byte) - PCEQH (Parallel Compare for Equal Halfword) - PCEQW (Parallel Compare for Equal Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-14-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)Philippe Mathieu-Daudé2-0/+78
Introduce the 'Parallel Extend Lower' opcodes: - PEXTLB (Parallel Extend Upper from Byte) - PEXTLH (Parallel Extend Upper from Halfword) - PEXTLW (Parallel Extend Upper from Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-13-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)Philippe Mathieu-Daudé2-0/+34
Introduce the PEXTUW opcode (Parallel Extend Upper from Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-12-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)Philippe Mathieu-Daudé2-0/+25
Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)Philippe Mathieu-Daudé2-0/+58
Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-16-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11hw/pci-host/raven: Add PCI_IO_BASE_ADDR definitionPhilippe Mathieu-Daudé1-4/+7
Rather than using the magic 0x80000000 number for the PCI I/O BAR physical address on the main system bus, use a definition. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210417103028.601124-6-f4bug@amsat.org>
2021-07-11hw/pci-host: Rename Raven ASIC PCI bridge as raven.cPhilippe Mathieu-Daudé5-4/+4
The ASIC PCI bridge chipset from Motorola is named 'Raven'. This chipset is used in the PowerPC Reference Platform (PReP), but not restricted to it. Rename it accordingly. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210417103028.601124-5-f4bug@amsat.org>
2021-07-09cpu: Add breakpoint tracepointsRichard Henderson2-4/+14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson12-18/+4
Since 6eea04347eb6, all tcg backends support goto_ptr. Remove the conditional, making support mandatory. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Log tb->cflags with -d execRichard Henderson1-3/+3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Split out log_cpu_execRichard Henderson1-27/+34
Split out CPU_LOG_EXEC and CPU_LOG_TB_CPU logging from cpu_tb_exec to a new function. Perform only one pc range check after a combined mask check. Use the new function in lookup_tb_ptr. This enables CPU_LOG_TB_CPU between indirectly chained tbs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Move tb_lookup to cpu-exec.cRichard Henderson2-50/+30
Now that we've moved helper_lookup_tb_ptr, the only user of tb-lookup.h is cpu-exec.c; merge the contents in. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.cRichard Henderson2-22/+30
This will allow additional code sharing. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/i386: Use cpu_breakpoint_test in breakpoint_handlerRichard Henderson1-9/+3
The loop is performing a simple boolean test for the existence of a BP_CPU breakpoint at EIP. Plus it gets the iteration wrong, if we happen to have a BP_GDB breakpoint at the same address. We have a function for this: cpu_breakpoint_test. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20210620062317.1399034-1-richard.henderson@linaro.org>
2021-07-09tcg: Fix prologue disassemblyRichard Henderson1-2/+2
In tcg_region_prologue_set, we reset TCGContext.code_gen_ptr. So do that after we've used it to dump the prologue contents. Fixes: b0a0794a0f16 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09util/guest-random: Fix size arg to tail memcpyMark Nelson1-1/+1
We know that in the body of this if statement i is less than len, so we really should be copying len - i bytes not i - len bytes. Fix this typo. Fixes: 8d8404f1564 ("util: Add qemu_guest_getrandom and associated routines") Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210709120600.11080-1-mdnelson8@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>