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2025-09-30lcitool: update, switch to f41Marc-André Lureau20-37/+79
Newer lcitool version has various fixes helping QEMU CI and this series. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250924120426.2158655-13-marcandre.lureau@redhat.com>
2025-09-30build-sys: cfi_debug and safe_stack are not compatibleMarc-André Lureau2-3/+6
It fails to link on fedora >= 41: /usr/bin/ld: /usr/bin/../lib/clang/20/lib/x86_64-redhat-linux-gnu/libclang_rt.safestack.a(safestack.cpp.o): in function `__sanitizer_internal_memcpy': (.text.__sanitizer_internal_memcpy+0x0): multiple definition of `__sanitizer_internal_memcpy'; /usr/bin/../lib/clang/20/lib/x86_64-redhat-linux-gnu/libclang_rt.ubsan_standalone.a(sanitizer_libc.cpp.o):(.text.__sanitizer_internal_memcpy+0x0): first defined here /usr/bin/ld: /usr/bin/../lib/clang/20/lib/x86_64-redhat-linux-gnu/libclang_rt.safestack.a(safestack.cpp.o): in function `__sanitizer_internal_memmove': (.text.__sanitizer_internal_memmove+0x0): multiple definition of `__sanitizer_internal_memmove'; /usr/bin/../lib/clang/20/lib/x86_64-redhat-linux-gnu/libclang_rt.ubsan_standalone.a(sanitizer_libc.cpp.o):(.text.__sanitizer_internal_memmove+0x0): first defined here /usr/bin/ld: /usr/bin/../lib/clang/20/lib/x86_64-redhat-linux-gnu/libclang_rt.safestack.a(safestack.cpp.o): in function `__sanitizer_internal_memset': (.text.__sanitizer_internal_memset+0x0): multiple definition of `__sanitizer_internal_memset'; /usr/bin/../lib/clang/20/lib/x86_64-redhat-linux-gnu/libclang_rt.ubsan_standalone.a(sanitizer_libc.cpp.o):(.text.__sanitizer_internal_memset+0x0): first defined here cfi_debug seems to pull ubsan which has conflicting symbols with safe_stack. See also: https://bugzilla.redhat.com/show_bug.cgi?id=2397265 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250924120426.2158655-12-marcandre.lureau@redhat.com>
2025-09-30tests/docker/common: print meson log on configure failureMarc-André Lureau1-1/+1
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250924120426.2158655-11-marcandre.lureau@redhat.com>
2025-09-30tests/docker: use fully qualified image name for emsdkMarc-André Lureau1-1/+1
Without it, at least it fails with podman on fc42: [1/6] STEP 1/15: FROM emscripten/emsdk:3.1.50 AS build-base Error: creating build container: short-name resolution enforced but cannot prompt without a TTY Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Message-ID: <20250924120426.2158655-10-marcandre.lureau@redhat.com>
2025-09-30tests/docker/common: print errors to stderrMarc-André Lureau1-2/+2
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250924120426.2158655-9-marcandre.lureau@redhat.com>
2025-09-30configure: set the bindgen cross targetMarc-André Lureau4-0/+110
Implement a bash version of rust-bindgen rust_to_clang_target() to convert from rust target to clang target. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250924120426.2158655-8-marcandre.lureau@redhat.com>
2025-09-30configure: fix rust meson configurationMarc-André Lureau1-1/+1
It was incorrectly set on the [host_machine] and caused error: File "/tmp/qemu-test/build/pyvenv/lib/python3.11/site-packages/mesonbuild/envconfig.py", line 281, in from_literal assert all(isinstance(v, str) for v in raw.values()), 'for mypy' AssertionError: for mypy Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250924120426.2158655-7-marcandre.lureau@redhat.com>
2025-09-30scripts/archive-source: use a bash arrayMarc-André Lureau1-8/+23
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250924120426.2158655-6-marcandre.lureau@redhat.com>
2025-09-30scripts/archive-source: silence subprojects downloadsMarc-André Lureau1-1/+1
It's too verbose. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250924120426.2158655-5-marcandre.lureau@redhat.com>
2025-09-30scripts/archive-source: speed up downloading subprojectsMarc-André Lureau1-2/+3
Running meson on each subproject is quite slow. According to Paolo, meson will run download tasks in parallel. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250924120426.2158655-4-marcandre.lureau@redhat.com>
2025-09-30gitlab-ci: fix 'needs' property type must be arrayMarc-André Lureau3-54/+54
The gitlab "Pipeline editor" has some warnings, and gitlab-ci-local fails. Read also from the docs https://docs.gitlab.com/ci/yaml/#needs "Supported values: An array of jobs (maximum of 50 jobs). An empty array ([]), to set the job to start as soon as the pipeline is created." Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250924120426.2158655-3-marcandre.lureau@redhat.com>
2025-09-30build-sys: require -lrt when no shm_open() in std libsMarc-André Lureau1-7/+9
Fail during configure time if the shm functions are missing, as required by oslib-posix.c. Note, we could further check the presence of the function in librt. This is a minor cleanup/improvement. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250924120426.2158655-2-marcandre.lureau@redhat.com>
2025-09-29hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errpJamin Lin1-14/+20
Refactor ast2700fc_ca35_init(), ast2700fc_ssp_init(), and ast2700fc_tsp_init() to take an Error **errp parameter and return a bool. Each function now reports failure through the error object and returns false. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed_ast27x0-fc: Drop dead return checksJamin Lin1-29/+14
1. object_property_set_link() can return false only when it fails, and it sets an error when it fails. Since passing &error_abort causes an abort, the function never returns false, and the return statement is effectively dead code. 2. object_property_set_int() is considered as a routine which shouldn't fail. So the common practice in models is to pass &error_abort and ignore the returned value. https://patchwork.kernel.org/project/qemu-devel/patch/20250717034054.1903991-3-jamin_lin@aspeedtech.com/#26540626 No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed: Move aspeed_load_vbootrom to common SoC codeJamin Lin3-30/+30
Move the vbootrom loader helper into common SoC code so it can be reused by all ASPEED boards, and decouple the API from AspeedMachineState. Specifically: - Move aspeed_load_vbootrom() to hw/arm/aspeed_soc_common.c and declare it in include/hw/arm/aspeed_soc.h. - Change the helper’s signature to take AspeedSoCState * instead of AspeedMachineState *. - Update aspeed_machine_init() call sites accordingly. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed: Move aspeed_install_boot_rom to common SoC codeJamin Lin3-20/+22
Move the boot ROM install helper into common SoC code so it can be reused by all ASPEED boards, and decouple the API from AspeedMachineState. Specifically: - Move aspeed_install_boot_rom() to hw/arm/aspeed_soc_common.c and declare it in include/hw/arm/aspeed_soc.h. - Change the helper’s signature to take AspeedSoCState * and a MemoryRegion * provided by the caller, instead of AspeedMachineState *. - Update aspeed_machine_init() call sites accordingly. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed: Move write_boot_rom to common SoC codeJamin Lin3-31/+35
Move the write_boot_rom helper from hw/arm/aspeed.c into hw/arm/aspeed_soc_common.c so it can be reused by all ASPEED machines. Export the API as aspeed_write_boot_rom() in include/hw/arm/aspeed_soc.h and update the existing call site to use the new helper. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC codeJamin Lin2-22/+23
Relocate aspeed_board_init_flashes() from hw/arm/aspeed.c into hw/arm/aspeed_soc_common.c so the helper can be reused by all ASPEED machines. The API was already declared in include/hw/arm/aspeed_soc.h; this change moves its implementation out of the machine file to keep aspeed.c cleaner. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29tests/functional/arm/test_aspeed_ast2600: Add PCIe and network testJamin Lin1-0/+21
Extend the AST2600 functional tests with PCIe and network checks. This patch introduces a new helper "do_ast2600_pcie_test()" that runs "lspci" on the emulated system and verifies the presence of the expected PCIe devices: - 80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600 - 80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge - 81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection To exercise the PCIe network device, the test adds: -device e1000e,netdev=net1,bus=pcie.0 -netdev user,id=net1 and assigns an IP address to the interface, verifying it with `ip addr`. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-14-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700Jamin Lin2-0/+75
Add PCIe Root Complex support to the AST2700 SoC model. The AST2700 A1 silicon revision provides three PCIe Root Complexes: PCIe0 with its PHY at 0x12C15000, config (H2X) block at 0x120E0000, MMIO window at 0x60000000, and GIC IRQ 56. PCIe1 with its PHY at 0x12C15800, config (H2X) block at 0x120F0000, MMIO window at 0x80000000, and GIC IRQ 57. PCIe2 with its PHY at 0x14C1C000, config (H2X) block at 0x140D0000, MMIO window at 0xA0000000, and IRQ routed through INTC4 bit 31 mapped to GIC IRQ 196. Each RC instantiates a PHY device, a PCIe config (H2X) bridge, and an MMIO alias region. The per-RC MMIO alias size is 0x20000000. The AST2700 A0 silicon revision does not support PCIe Root Complexes, so pcie_num is set to 0 in that variant. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to ↵Jamin Lin1-0/+2
AST2700 AST2700 does not implement a PCIe Root Device; each RC exposes a single PCIe Root Port at devfn 0:0.0. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocksJamin Lin2-0/+161
Introduce PCIe config (H2X) support for the AST2700 SoC. Unlike the AST2600, the AST2700 provides three independent Root Complexes, each with its own H2X (AHB to PCIe bridge) register block of size 0x100. All RCs use the same MSI address (0x000000F0). The H2X block includes two different access paths: 1. CFGI (internal bridge): used to access the host bridge itself, always with BDF=0. The AST2700 controller simplifies the design by exposing only one register (H2X_CFGI_TLP) with fields for ADDR[15:0], BEN[19:16], and WR[20]. This is not a full TLP descriptor as in the external case. For QEMU readability and code reuse, the model converts H2X_CFGI_TLP into a standard TLP TX descriptor with BDF forced to 0 and then calls the existing helpers aspeed_pcie_cfg_readwrite() and aspeed_pcie_cfg_translate_write(). 2. CFGE (external EP access): used to access external endpoints. The AST2700 design provides H2X_CFGE_TLP1 and a small FIFO at H2X_CFGE_TLPN. For reads, TX DESC0 is stored in TLP1 and DESC1/DESC2 in TLPN FIFO slots. For writes, TX DESC0 is stored in TLP1, DESC1/DESC2 in TLPN FIFO[0..1], and TX write data in TLPN FIFO[2]. The implementation extends AspeedPCIECfgState with a small FIFO and index, wires up new register definitions for AST2700, and adds a specific ops table and class (TYPE_ASPEED_2700_PCIE_CFG). The reset handler clears the FIFO state. Interrupt and MSI status registers are also supported. This provides enough modeling for firmware and drivers to use any of the three PCIe RCs on AST2700 with their own dedicated H2X config window, while reusing existing TLP decode helpers in QEMU. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add AST2700 PCIe PHYJamin Lin2-0/+40
Introduce a PCIe Host Controller PHY model for AST2700. This adds an AST2700 specific PHY type (TYPE_ASPEED_2700_PCIE_PHY) with a 0x800 byte register space and link-status bits compatible with the firmware’s expectations. AST2700 provides three PCIe RCs; PCIe0 and PCIe1 are GEN4, PCIe2 is GEN2. The PHY exposes: PEHR_2700_LINK_GEN2 at 0x344, bit 18 indicates GEN2 link up PEHR_2700_LINK_GEN4 at 0x358, bit 8 indicates GEN4 link up In real hardware these GEN2/GEN4 link bits are mutually exclusive. QEMU does not model GEN2 vs GEN4 signaling differences, so the reset handler sets both bits to 1. This keeps the model simple and lets firmware see the link as up; firmware will read the appropriate register per RC port to infer the intended mode. The header gains TYPE_ASPEED_2700_PCIE_PHY; the new class derives from TYPE_ASPEED_PCIE_PHY, sets nr_regs to 0x800 >> 2, and installs an AST2700 reset routine that programs the class code (0x06040011) and the GEN2/GEN4 status bits. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)Jamin Lin2-0/+75
Wire up the PCIe Root Complex in the AST2600 SoC model. According to the AST2600 firmware driver, only the RC_H controller is supported. RC_H uses PCIe PHY1 at 0x1e6ed200 and the PCIe config (H2X) register block at 0x1e770000. The RC_H MMIO window is mapped at 0x70000000–0x80000000. RC_L is not modeled. The RC_H interrupt is wired to IRQ 168. Only RC_H is realized and connected to the SoC interrupt controller. The SoC integration initializes PCIe PHY1, instantiates a single RC instance, wires its MMIO regions, and connects its interrupt. An alias region is added to map the RC MMIO space into the guest physical address space. This provides enough functionality for firmware and guest drivers to discover and use the AST2600 RC_H Root Complex while leaving RC_L unimplemented. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed: Wire up PCIe devices in SoC modelJamin Lin1-0/+13
Add PCIe controller and PHY instances to the Aspeed SoC state and device enum. This prepares the SoC model to host PCIe Root Complexes and their associated PHYs. Although the AST2600 supports only a single Root Complex, the AST2700 provides three Root Complexes. For this reason, the model defines arrays of three PCIe config/PHY objects and enumerates three PCIe device IDs so that both SoCs can be represented consistently. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address spaceJamin Lin3-0/+145
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes. On AST2700 all RCs use the same MSI address, and the MSI target is PCI system memory (not normal DRAM). If the MSI window were mapped into real system RAM, an endpoint's write could be observed by other RCs and spuriously trigger their interrupts. To avoid this, each RC now owns an isolated IOMMU root AddressSpace that contains a small MSI window and a DRAM alias region for normal DMA. The MSI window captures writes and asserts the RC IRQ. MSI status bits are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The default MSI address is set to 0x1e77005c and can be overridden via the msi-addr property. This keeps MSI traffic contained within each RC while preserving normal DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when multiple RCs use the same MSI target address. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurableJamin Lin2-0/+61
Introduce an ASPEED PCIe Root Port and wire it under the RC. The root port is modeled as TYPE_ASPEED_PCIE_ROOT_PORT (subclass of TYPE_PCIE_ROOT_PORT). Key changes: - Add TYPE_ASPEED_PCIE_ROOT_PORT (PCIESlot-based) with vendor/device IDs and AER capability offset. - Extend AspeedPCIERcState to embed a root_port instance and a configurable rp_addr. - Add "rp-addr" property to the RC to place the root port at a specific devfn on the root bus. - Set the root port's "chassis" property to ensure a unique chassis per RC. - Extend AspeedPCIECfgClass with rc_rp_addr defaulting to PCI_DEVFN(8,0). Rationale: - AST2600 places the root port at 80:08.0 (bus 0x80, dev 8, fn 0). - AST2700 must place the root port at 00:00.0, and it supports three RCs. Each root port must therefore be uniquely identifiable; uses the PCIe "chassis" ID for that. - Providing a configurable "rp-addr" lets platforms select the correct devfn per SoC family, while the "chassis" property ensures uniqueness across multiple RC instances on AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe Root Device supportJamin Lin2-0/+67
Introduce a PCIe Root Device for AST2600 platform. The AST2600 root complex exposes a PCIe root device at bus 80, devfn 0. This root device is implemented as a child of the PCIe RC and modeled as a host bridge PCI function (class_id = PCI_CLASS_BRIDGE_HOST). Key changes: - Add a new device type "aspeed.pcie-root-device". - Instantiate the root device as part of AspeedPCIERcState. - Initialize it during RC realize() and attach it to the root bus. - Mark the root device as non-user-creatable. - Add RC boolean property "has-rd" to control whether the Root Device is created (platforms can enable/disable it as needed). Note: Only AST2600 implements this PCIe root device. AST2700 does not provide one. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridgeJamin Lin3-0/+484
Introduce PCIe config and host bridge model for the AST2600 platform. This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller with a 0x100 byte register space. The register layout is shared between two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff for RC_H. Only RC_H is modeled in this implementation. The RC_H bus uses bus numbers in the 0x80–0xff range instead of the standard root bus 0x00. To allow the PCI subsystem to discover devices, the host bridge logic remaps the root bus number back to 0x00 whenever the configured bus number matches the "bus-nr" property. New MMIO callbacks are added for the H2X config space: - aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register accesses. - aspeed_pcie_cfg_readwrite() provides configuration read/write support. - aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for write operations. The reset handler initializes the H2X register block with default values as defined in the AST2600 datasheet. Additional changes: - Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC). - Wire up interrupt propagation via aspeed_pcie_rc_set_irq(). - Add tracepoints for config read/write and INTx handling. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci-host/aspeed: Add AST2600 PCIe PHY modelJamin Lin6-0/+211
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging. Key changes: 1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses. 2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED. 3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses. 4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up. This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension. This commit is the starting point of the series to introduce ASPEED PCIe Root Complex (RC) support. Based on previous work from Cédric Le Goater, the following commits in this series extend and refine the implementation: - Add a PCIe Root Port so that devices can be attached without requiring an extra bridge. - Restrict the Root Port device instantiation to the AST2600 platform. - Integrate aspeed_cfg_translate_write() to support both AST2600 and AST2700. - Add MSI support and a preliminary RC IOMMU address space. - Fix issues with MSI interrupt clearing. - Extend support to the AST2700 SoC. - Drop the AST2600 RC_L support. - Introduce PCIe RC functional tests covering both AST2600 and AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/pci/pci_ids: Add PCI vendor ID for ASPEEDJamin Lin1-0/+2
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29tests/functional/arm: Add AST2600 boot test with generated OTP imageKane-Chen-AS1-0/+15
Add a functional test that boots an AST2600 machine with a generated OTP image. The test verifies that OTP contents are read during early boot and that the system reaches the expected console prompt. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250917035917.4141723-4-kane_chen@aspeedtech.com [ clg: checkpath fixes ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29tests/functional/arm: Add AST1030 boot test with generated OTP imageKane-Chen-AS1-4/+20
Add a functional test that boots an AST1030 machine with a generated OTP image. The test verifies that OTP contents are read during early boot and that the system reaches the expected console prompt. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250917035917.4141723-3-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29tests/functional/arm: Add helper to generate OTP imagesKane-Chen-AS1-0/+8
Add a small helper that generates OTP images at test time. This lets multiple test cases create default OTP contents without shipping prebuilt fixtures and keeps the tests self-contained. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250917035917.4141723-2-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evbJamin Lin2-3/+3
This patch moves the "ast2700-evb" alias from the A0 to A1. The A0 machine remains available via its explicit name ("ast2700a0-evb"), while functional tests are updated to target A0 by name instead of relying on the generic alias. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250902062550.3797040-1-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29docs/system/arm/aspeed: Document OTP memory optionsKane-Chen-AS1-0/+31
Add documentation for the OTP memory module used by AST2600 and AST1030 SoCs, and describe options for using a pre-generated image or an internal buffer. Include example commands for configuration and image generation. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-11-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registersKane-Chen-AS2-0/+42
Extend OTP command handling to recognize specific voltage mode register addresses and emulate the expected hardware behavior. Without this change, legitimate voltage mode change requests would be incorrectly reported as "Unknown command" and logged as an error. This implementation does not perform actual mode changes, but ensures that valid requests are accepted and ignored as per hardware behavior. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-9-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/misc/aspeed_sbc: Add CAMP2 support for OTP data readsKane-Chen-AS1-0/+27
The OTP space contains three types of entries: data, conf, and strap. Data entries consist of two DWORDs, while the other types contain only one DWORD. This change adds the R_CAMP2 register (0x024 / 4) to store the second DWORD when reading from the OTP data region. With this enhancement, OTP reads now correctly return both DWORDs for data entries via the CAMP registers, along with improved address validation and error handling. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-8-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCsKane-Chen-AS3-1/+18
The has_otp attribute is enabled in the SBC subclasses for AST1030 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-7-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/nvram/aspeed_otp: Add OTP programming semantics and tracingKane-Chen-AS2-1/+84
Implement correct OTP programming behavior for Aspeed OTP: - Support read-modify-write flow with one-way bit programming: * prog_bit uses 0s as the "to-be-programmed" mask. * Even-indexed words: 0->1, odd-indexed words: 1->0. * Reject non-programmable requests and log conflicts. - Enable unaligned accesses in MemoryRegionOps. Since each OTP address maps to a 1DW (4B) or 2DW (8B) block in the backing store, upper-layer accesses may be unaligned to block boundaries. This matches the irreversible, word-parity-dependent programming rules of Aspeed SoCs and exposes changes via QEMU trace events. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-6-kane_chen@aspeedtech.com [ clg: Fixed PRIx64 format in aspeed_otp_write() ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/nvram/aspeed_otp: Add 'drive' property to support block backendKane-Chen-AS1-1/+14
This patch introduces a 'drive' property to the Aspeed OTP device, allowing it to be backed by a block device. Users can now preload OTP data via QEMU CLI using a block backend. Example usage: ./qemu-system-arm \ -blockdev driver=file,filename=otpmem.img,node-name=otp \ -global aspeed-otp.drive=otp \ ... If the drive is provided, its content will be loaded as the initial OTP state. Otherwise, an internal memory buffer will be used. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-5-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCsKane-Chen-AS2-1/+3
The has_otp attribute is enabled in the SBC subclasses for AST2600 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-4-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBCKane-Chen-AS3-0/+121
This patch connects the aspeed.otp device to the ASPEED Secure Boot Controller (SBC) model. It implements OTP memory access via the SBC's command interface and enables emulation of secure fuse programming flows. The following OTP commands are supported: - READ: reads a 32-bit word from OTP memory into internal registers - PROG: programs a 32-bit word value to the specified OTP address Trace events are added to observe read/program operations and command handling flow. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-3-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-29hw/nvram/aspeed_otp: Add ASPEED OTP memory device modelKane-Chen-AS3-0/+136
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage. The OTP memory can operate with an internal memory buffer. The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-2-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-09-28target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear maskDenis Sergeev1-1/+1
In gen_mcrfs() the FPSCR nibble mask is computed as: `~((0xF << shift) & FP_EX_CLEAR_BITS)` Here, 0xF is of type int, so the left shift is performed in 32-bit signed arithmetic. For bfa=0 we get shift=28, and (0xF << 28) = 0xF0000000, which is not representable as a 32-bit signed int. Static analyzers flag this as a potential integer overflow. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Denis Sergeev <zeff@altlinux.org> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250915080118.29898-1-zeff@altlinux.org Message-ID: <20250915080118.29898-1-zeff@altlinux.org>
2025-09-28target/ppc: Deprecate Power8E and Power8NVLAditya Gupta2-4/+13
Power8E and Power8NVL variants are not of much use in QEMU now, and not being maintained either. Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit to be exact: commit c5424f683ee3 ("Remove support for POWER8 DD1") Deprecate the 8E and 8NVL variants. Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Anushree Mathur <anushree.mathur@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250607110412.2342511-3-adityag@linux.ibm.com Message-ID: <20250607110412.2342511-3-adityag@linux.ibm.com>
2025-09-28target/ppc: Introduce macro for deprecating PowerPC CPUsAditya Gupta2-2/+17
QEMU has a way to deprecate CPUs by setting the 'deprecation_note' in CPUClass. Currently PowerPC CPUs don't use this deprecation process. Introduce 'POWERPC_DEPRECATED_CPU' macro to deprecate particular PowerPC CPUs in future. With the change, QEMU will print a warning like below when the deprecated CPU/Chips are used (example output if power8nvl is deprecated): $ ./build/qemu-system-ppc64 -M powernv8 --cpu power8nvl -nographic qemu-system-ppc64: warning: CPU model power8nvl_v1.0-powerpc64-cpu is deprecated -- CPU is unmaintained. ... Also, print '(deprecated)' for deprecated CPUs in 'qemu-system-ppc64 --cpu ?' (example output if power8nvl is deprecated): $ ./build/qemu-system-ppc64 --cpu help ... power8e (alias for power8e_v2.1) power8nvl_v1.0 PVR 004c0100 (deprecated) power8nvl (alias for power8nvl_v1.0) power8_v2.0 PVR 004d0200 ... Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Anushree Mathur <anushree.mathur@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250607110412.2342511-2-adityag@linux.ibm.com Message-ID: <20250607110412.2342511-2-adityag@linux.ibm.com>
2025-09-28target/ppc: Move remaining floating-point move instructions to decodetree.Chinmay Rath3-40/+32
Move below instructions to decodetree specification: fcpsgn, fmrg{e, o}w : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-5-rathc@linux.ibm.com Message-ID: <20250619095840.369351-5-rathc@linux.ibm.com>
2025-09-28target/ppc: Move floating-point move instructions to decodetree.Chinmay Rath3-63/+28
Move below instructions to decodetree specification: f{mr, neg, abs, nabs} : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-4-rathc@linux.ibm.com Message-ID: <20250619095840.369351-4-rathc@linux.ibm.com>
2025-09-28target/ppc: Move floating-point compare instructions to decodetree.Chinmay Rath5-38/+22
Move below instructions to decodetree specification : fcmp{u, o} : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-3-rathc@linux.ibm.com Message-ID: <20250619095840.369351-3-rathc@linux.ibm.com>