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2021-08-25target/mips: Define gen_helper() macros in translate.hPhilippe Mathieu-Daudé2-12/+12
To be able to split some code calling the gen_helper() macros out of the huge translate.c, we need to define them in the 'translate.h' local header. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-9-f4bug@amsat.org>
2021-08-25target/mips: Use tcg_constant_i32() in generate_exception_err()Philippe Mathieu-Daudé1-5/+2
excp/err are temporaries input, so we can replace tcg_const_i32() calls by tcg_constant_i32() equivalent. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-8-f4bug@amsat.org>
2021-08-25target/mips: Inline gen_helper_0e0i()Philippe Mathieu-Daudé1-6/+2
gen_helper_0e0i() is one-line long and is only used twice: simply inline it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>
2021-08-25target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macrosPhilippe Mathieu-Daudé1-5/+1
gen_helper_1e1i() is one-line long and is used in one place: simply inline it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-6-f4bug@amsat.org>
2021-08-25target/mips: Simplify gen_helper() macros by using tcg_constant_i32()Philippe Mathieu-Daudé1-15/+5
In all call sites the last argument is always used as a read-only value, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-5-f4bug@amsat.org>
2021-08-25target/mips: Use tcg_constant_i32() in gen_helper_0e2i()Philippe Mathieu-Daudé1-12/+2
$rt register is used read-only, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>
2021-08-25target/mips: Remove gen_helper_1e2i()Philippe Mathieu-Daudé1-6/+0
gen_helper_1e2i() is unused since commit 33a07fa2db6 ("target/mips: reimplement SC instruction emulation and use cmpxchg"), remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-3-f4bug@amsat.org>
2021-08-25target/mips: Remove gen_helper_0e3i()Philippe Mathieu-Daudé1-6/+0
gen_helper_0e3i() is unused since commit 895c2d04359 ("target-mips: switch to AREG0 free mode"), remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-2-f4bug@amsat.org>
2021-08-25target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXTPhilippe Mathieu-Daudé1-2/+0
We already call check_cp1_enabled() earlier in the "pre-conditions" checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue. Remove the duplicated calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210816001031.1720432-1-f4bug@amsat.org>
2021-08-25target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddrPhilippe Mathieu-Daudé1-1/+1
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements 48 virtual address bits in each 64-bit segment, not 40. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>
2021-08-25target/mips: Document Loongson-3A CPU definitionsPhilippe Mathieu-Daudé1-2/+2
Document the cores on which each Loongson-3A CPU is based (see commit af868995e1b, "target/mips: Add Loongson-3 CPU definition"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210813110149.1432692-2-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MSA* opcodes to decodetreePhilippe Mathieu-Daudé3-53/+14
Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MUL* opcodes to decodetreePhilippe Mathieu-Daudé3-24/+18
Convert the following Integer Multiply-Accumulate opcodes: * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO * MULSHI Multiply, negate, and move HI * MULSHIU Unsigned multiply, negate, and move HI * MULSU Unsigned multiply, negate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-7-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MACC* opcodes to decodetreePhilippe Mathieu-Daudé3-16/+42
Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
2021-08-25target/mips: Introduce decodetree structure for NEC Vr54xx extensionPhilippe Mathieu-Daudé5-0/+33
The decoder is called but doesn't decode anything. This will ease reviewing the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801235926.3178085-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.cPhilippe Mathieu-Daudé3-118/+143
Extract NEC Vr54xx helpers from op_helper.c to a new file: 'vr54xx_helper.c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-14-f4bug@amsat.org>
2021-08-25target/mips: Extract NEC Vr54xx helper definitionsPhilippe Mathieu-Daudé2-15/+27
Extract the NEC Vr54xx helper definitions to 'vendor-vr54xx_helper.h'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-15-f4bug@amsat.org>
2021-08-25target/mips: Introduce generic TRANS() macro for decodetree helpersPhilippe Mathieu-Daudé1-0/+8
Plain copy/paste of the TRANS() macro introduced in the PPC commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer loads to decodetree") to the MIPS target. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210808173018.90960-2-f4bug@amsat.org>
2021-08-25target/mips: Rename 'rtype' as 'r'Philippe Mathieu-Daudé6-46/+46
We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Merge 32-bit/64-bit Release6 decodetree definitionsPhilippe Mathieu-Daudé4-40/+19
We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Decode vendor extensions before MIPS ISAsPhilippe Mathieu-Daudé1-3/+5
In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree") we misplaced the decoder call. Move it to the correct place. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Simplify PREF opcodePhilippe Mathieu-Daudé1-6/+2
check_insn() checks for any bit in the set, and INSN_R5900 is just another bit added to the set. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-2-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Remove JR opcode unused argumentsPhilippe Mathieu-Daudé1-1/+1
JR opcode (Jump Register) only takes 1 argument, $rs. JALR (Jump And Link Register) takes 3: $rs, $rd and $hint. Commit 6af0bf9c7c3 added their processing into decode_opc() as: case 0x08 ... 0x09: /* Jumps */ gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa); having both opcodes handled in the same function: gen_compute_branch. Per JR encoding, both $rd and $hint ('sa') are decoded as zero. Later this code got extracted to decode_opc_special(), commit 7a387fffce5 used definitions instead of magic values: case OPC_JR ... OPC_JALR: gen_compute_branch(ctx, op1, rs, rd, sa); Finally commit 0aefa33318b moved OPC_JR out of decode_opc_special, to a new 'decode_opc_special_legacy' function: @@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) + case OPC_JR: + gen_compute_branch(ctx, op1, 4, rs, rd, sa); + break; @@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) - case OPC_JR ... OPC_JALR: + case OPC_JALR: gen_compute_branch(ctx, op1, 4, rs, rd, sa); break; Since JR is now handled individually, it is pointless to decode and pass it unused arguments. Replace them by simple zero value to avoid confusion with this opcode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210730225507.2642827-1-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25Open 6.2 development treePeter Maydell1-1/+1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-24Update version for v6.1.0 releasePeter Maydell1-1/+1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-17Update version for v6.1.0-rc4 releasePeter Maydell1-1/+1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-17softmmu/physmem: fix wrong assertion in qemu_ram_alloc_internal()David Hildenbrand1-1/+0
When adding RAM_NORESERVE, we forgot to remove the old assertion when adding the updated one, most probably when reworking the patches or rebasing. We can easily crash QEMU by adding -object memory-backend-ram,id=mem0,size=500G,reserve=off to the QEMU cmdline: qemu-system-x86_64: ../softmmu/physmem.c:2146: qemu_ram_alloc_internal: Assertion `(ram_flags & ~(RAM_SHARED | RAM_RESIZEABLE | RAM_PREALLOC)) == 0' failed. Fix it by removing the old assertion. Fixes: 8dbe22c6868b ("memory: Introduce RAM_NORESERVE and wire it up in qemu_ram_mmap()") Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-id: 20210805092350.31195-1-david@redhat.com Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Xu <peterx@redhat.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-17qapi/machine.json: Remove zero value reference from SMPConfiguration ↵Andrew Jones1-1/+1
documentation Commit 1e63fe685804 ("machine: pass QAPI struct to mc->smp_parse") introduced documentation stating that a zero input value for an SMP parameter indicates that its value should be automatically configured. This is indeed how things work today, but we'd like to change that. Avoid documenting behaviors we want to leave undefined for the time being, giving us freedom to change it later. Fixes: 1e63fe685804 ("machine: pass QAPI struct to mc->smp_parse") Signed-off-by: Andrew Jones <drjones@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-13hw/core: fix error checking in smp_parseDaniel P. Berrangé1-1/+1
machine_set_smp() mistakenly checks 'errp' not '*errp', and so thinks there is an error every single time it runs. This causes it to jump to the end of the method, skipping the max CPUs checks. The caller meanwhile sees no error and so carries on execution. The result of all this is: $ qemu-system-x86_64 -smp -1 qemu-system-x86_64: GLib: ../glib/gmem.c:142: failed to allocate 481036337048 bytes instead of $ qemu-system-x86_64 -smp -1 qemu-system-x86_64: Invalid SMP CPUs -1. The max CPUs supported by machine 'pc-i440fx-6.1' is 255 This is a regression from commit fe68090e8fbd6e831aaf3fc3bb0459c5cccf14cf Author: Paolo Bonzini <pbonzini@redhat.com> Date: Thu May 13 09:03:48 2021 -0400 machine: add smp compound property Closes: https://gitlab.com/qemu-project/qemu/-/issues/524 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210812175353.4128471-1-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-13hw/core: Add missing return on errorPhilippe Mathieu-Daudé1-0/+1
If dies is not supported by this machine's CPU topology, don't keep processing options and return directly. Fixes: 0aebebb561c ("machine: reject -smp dies!=1 for non-PC machines") Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210813112608.1452541-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-13target/i386: Fixed size of constant for WindowsLara Lazier2-2/+2
~0UL has 64 bits on Linux and 32 bits on Windows. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512 Reported-by: Volker Rümelin <vr_qemu@t-online.de> Signed-off-by: Lara Lazier <laramglazier@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210812111056.26926-1-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-12Hexagon (disas/hexagon.c) fix memory leak for early exit casesTaylor Simpson1-1/+2
Don't allocate the string until error conditions have been checked Fixes: a00cfed0e ("Hexagon (disas) disassembler") Eliminate Coverity CID 1460121 (Resource leak) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daud? <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-08-11docs/about/removed-features: Document removed machines from older QEMU versionsThomas Huth1-2/+18
These machines had been removed in the QEMU v2.6 up to 4.0 time frame. Message-Id: <20210811084103.74832-7-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11docs/about/removed-features: Document removed devices from older QEMU versionsThomas Huth1-0/+11
These devices had been removed/replaced in QEMU v2.12 and v4.0. Message-Id: <20210811084103.74832-6-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11docs/about/removed-features: Document removed HMP commands from QEMU v2.12Thomas Huth1-0/+11
These HMP commands had been removed/replaced in QEMU v2.12. Still, some people might want to update from older versions to the recent QEMU version, so we should give some recommendations for the replacements in our documentation. Message-Id: <20210811084103.74832-5-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11docs/about/removed-features: Document removed CLI options from QEMU v3.1Thomas Huth1-0/+67
These CLI options had been removed/replaced in QEMU v3.1. Still, some people might want to update from older versions to the recent QEMU version, so we should give some recommendations for the replacements in our documentation. Message-Id: <20210811084103.74832-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11docs/about/removed-features: Document removed CLI options from QEMU v3.0Thomas Huth1-0/+35
These CLI options had been removed/replaced in QEMU v3.0. Still, some people might want to update from older versions to the recent QEMU version, so we should give some recommendations for the replacements in our documentation. Message-Id: <20210811084103.74832-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11docs/about/removed-features: Document removed CLI options from QEMU v2.12Thomas Huth1-2/+37
These CLI options had been removed/replaced in QEMU v2.12. Still, some people might want to update from older versions to the recent QEMU version, so we should give some recommendations for the replacements in our documentation. Message-Id: <20210811084103.74832-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11fuzz: avoid building twice, when running on gitlabAlexander Bulekov1-11/+13
On oss-fuzz, we build twice, to put together a build that is portable to the runner containers. On gitlab ci, this is wasteful and contributes to timeouts on the build-oss-fuzz job. Avoid building twice on gitlab, at the remote cost of potentially missing some cases that break oss-fuzz builds. Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-Id: <20210809111621.54454-1-alxndr@bu.edu> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11tests/qtest/vhost-user-blk-test: Check whether qemu-storage-daemon is availableThomas Huth1-0/+8
The vhost-user-blk-test currently hangs if QTEST_QEMU_STORAGE_DAEMON_BINARY points to a non-existing binary. Let's improve this situation by checking for the availability of the binary first, so we can fail gracefully if it is not accessible. Message-Id: <20210811095949.133462-1-thuth@redhat.com> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11storage-daemon: Add missing build dependency to the vhost-user-blk-testThomas Huth2-6/+9
vhost-user-blk-test needs the qemu-storage-daemon, otherwise it currently hangs. So make sure that we build the daemon before running the tests. Message-Id: <20210811094705.131314-1-thuth@redhat.com> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11gitlab: skip many more targets in windows cross buildsDaniel P. Berrangé2-1/+5
The windows cross builds still take way too long in gitlab CI, so need more targets to be skipped. We don't want to hurt coverage of other cross builds more though, so we let jobs fine tune with a new env variale $CROSS_SKIP_TARGETS. We take the set of targets that are considered relatively niche or very old architectures, and skip approx half of them in win32 builds and the other half of them in win64. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210810140653.3969823-3-berrange@redhat.com> [thuth: Swapped the "CROSS_SKIP_TARGETS:" lines as suggested by philmd] Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-11MAINTAINERS: update virtio-gpu entry.Gerd Hoffmann1-2/+2
New maintainer wanted. Downgrade status to "Odd Fixes" for now. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-8-kraxel@redhat.com>
2021-08-11MAINTAINERS: update virtio-input entry.Gerd Hoffmann1-1/+1
New maintainer wanted. Downgrade status to "Odd Fixes" for now. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-7-kraxel@redhat.com>
2021-08-11MAINTAINERS: update usb entries.Gerd Hoffmann1-2/+2
New maintainer wanted. Switch role to "Reviewer" for usb-serial, downgrade status to "Odd Fixes" for everything else. Cc: Samuel Thibault <samuel.thibault@ens-lyon.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-6-kraxel@redhat.com>
2021-08-11MAINTAINERS: update spice entry.Gerd Hoffmann1-1/+1
New maintainer wanted. Downgrade status to "Odd Fixes" for now. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-5-kraxel@redhat.com>
2021-08-11MAINTAINERS: update audio entry.Gerd Hoffmann1-1/+1
New maintainer wanted. Downgrade status to "Odd Fixes" for now. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-4-kraxel@redhat.com>
2021-08-11MAINTAINERS: update sockets entry.Gerd Hoffmann1-1/+0
I have not touched the code for years. Make the entry match reality and drop my name. Cc: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-3-kraxel@redhat.com>
2021-08-11MAINTAINERS: update edk2 entry.Gerd Hoffmann1-0/+1
I want keep an eye on the edk2 things happening in qemu. Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210810083450.2377374-2-kraxel@redhat.com>
2021-08-11gitlab: exclude sparc-softmmu and riscv32-softmmu from cross buildsDaniel P. Berrangé1-1/+2
We need to cut down compile time by excluding more targets. Both these targets still have their 64-bit variant enabled, so the loss of coverage is mitigated to some degree. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210810140653.3969823-2-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>