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2019-03-04s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDEDDavid Hildenbrand4-15/+44
With the floating-point extension facility, LOAD ROUNDED has a rounding mode specification and the inexact-exception control (XxC). Handle them just like e.g. LOAD FP INTEGER. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Implement XxC and checks for most FP instructionsDavid Hildenbrand2-126/+247
With the floating-point extension facility - CONVERT FROM LOGICAL - CONVERT TO LOGICAL - CONVERT TO FIXED - CONVERT FROM FIXED - LOAD FP INTEGER have both, a rounding mode specification and the inexact-exception control (XxC). Other instructions will be handled separatly. Check for valid rounding modes and forward also the XxC (via m4). To avoid a lot of boilerplate code and changes to the helpers, combine both, the m3 and m4 field in a combined 32 bit TCG variable. Perform checks at a central place, taking in account if the m3 or m4 field was ignore before the floating-point extension facility was introduced. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-13-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Prepare for IEEE-inexact-exception control (XxC)David Hildenbrand1-57/+57
Some instructions allow to suppress IEEE inexact exceptions. z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions" IEEE-inexact-exception control (XxC): Bit 1 of the M4 field is the XxC bit. If XxC is zero, recogni- tion of IEEE-inexact exception is not suppressed; if XxC is one, recognition of IEEE-inexact excep- tion is suppressed. Especially, handling for overflow/unerflow remains as is, inexact is reported along z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions" For example, the IEEE-inexact-exception control (XxC) has no effect on the DXC; that is, the DXC for IEEE- overflow or IEEE-underflow exceptions along with the detail for exact, inexact and truncated, or inexact and incremented, is reported according to the actual con- dition. Follow up patches will wire it correctly up for the applicable instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Refactor saving/restoring the bfp rounding modeDavid Hildenbrand2-43/+71
We want to reuse this in the context of vector instructions. So use better matching names and introduce s390_restore_bfp_rounding_mode(). While at it, add proper newlines. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Check for exceptions in SET BFP ROUNDING MODEDavid Hildenbrand4-35/+39
Let's split handling of BFP/DFP rounding mode configuration. Also, let's not reuse the sfpc handler, use a separate handler so we can properly check for specification exceptions for SRNMB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modesDavid Hildenbrand2-5/+19
We already forward the 3 bits correctly in the translation functions. We also have to handle them properly and check for specification exceptions. Setting an invalid rounding mode (BFP only, all DFP rounding modes) results in a specification exception. Setting unassigned bits in the fpc, results in a specification exception. This fixes LOAD FPC (AND SIGNAL), SET FPC (AND SIGNAL). Also for, SET BFP ROUNDING MODE, 3-bit rounding mode is now explicitly checked. Note: TCG_CALL_NO_WG is required for sfpc handler, as we now inject exceptions. We won't be modeling abscence of the "floating-point extension facility" for now, not necessary as most take the facility for granted without checking. z14 PoP, 9-23, "LOAD FPC" When the floating-point extension facility is installed, bits 29-31 of the second operand must specify a valid BFP rounding mode and bits 6-7, 14-15, 24, and 28 must be zero; otherwise, a specification exception is recognized. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-9-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Fix simulated-IEEE exceptionsDavid Hildenbrand1-0/+13
The trap is triggered based on priority of the enabled signaling flags. Only overflow and underflow allow a concurrent inexact exception. z14 PoP, 9-33, Figure 9-21 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Refactor SET FPC AND SIGNAL handlingDavid Hildenbrand1-10/+12
We can directly work on the uint64_t value, no need for a temporary uint32_t value. Also cleanup and shorten the comments. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Hide IEEE underflows in some scenariosDavid Hildenbrand1-0/+13
IEEE underflows are not reported when the mask bit is off and we don't also have an inexact exception. z14 PoP, 9-20, "IEEE Underflow": An IEEE-underflow exception is recognized for an IEEE target when the tininess condition exists and either: (1) the IEEE-underflow mask bit in the FPC register is zero and the result value is inexact, or (2) the IEEE-underflow mask bit in the FPC register is one. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Fix parts of IEEE exception handlingDavid Hildenbrand1-6/+32
Many things are wrong and some parts cannot be fixed yet. Fix what we can fix easily and add two FIXMEs: The fpc flags are not updated in case an exception is actually injected. Inexact exceptions have to be handled separately, as they are the only exceptions that can coexist with underflows and overflows. I reread the horribly complicated chapters in the PoP at least 5 times and hope I got it right. For references: - z14 PoP, 9-18, "IEEE Exceptions" - z14 PoP, 19-9, Figure 19-8 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Factor out conversion of softfloat exceptionsDavid Hildenbrand2-12/+20
We want to reuse that function in vector instruction context. While at it, cleanup the code, using defines for magic values and avoiding the handcrafted bit conversion. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Fix rounding from float128 to uint64_t/uint32_tDavid Hildenbrand1-6/+2
Let's use the proper conversion functions now that we have them. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Fix TEST DATA CLASS instructionsDavid Hildenbrand1-50/+35
Let's detect normal and denormal ("subnormal") numbers reliably. Also test for quiet NaN's. As only one class is possible, test common cases first. While at it, use a better check to test for the mask bits in the data class mask. The data class mask has 12 bits, whereby bit 0 is the leftmost bit and bit 11 the rightmost bit. In the PoP an easy to read table with the numbers is provided for the VECTOR FP TEST DATA CLASS IMMEDIATE instruction, the table for TEST DATA CLASS is more confusing as it is based on 64 bit values. Factor the checks out into separate functions, as they will also be needed for floating point vector instructions. We can use a makro to generate the functions. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-2-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARYDavid Hildenbrand5-0/+31
Use a new CC helper to calculate the CC lazily if needed. While the PoP mentions that "A 32-bit unsigned binary integer" is placed into the first operand, there is no word telling that the other 32 bits (high part) are left untouched. Maybe the other 32-bit are unpredictable. So store 64 bit for now. Bit magic courtesy of Richard. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-8-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFPDavid Hildenbrand2-0/+8
Nice trick to load a 32 bit value into vector element 0 (32 bit element size) from memory, zeroing out element1. The short HFP to long HFP conversion really only is a shift. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()David Hildenbrand1-15/+26
Also properly wrap in 24bit mode. While at it, convert the comment (and drop the comment about fundamental TCG optimizations). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Factor out vec_full_reg_offset()David Hildenbrand1-2/+7
We'll use that a lot along with gvec helpers, to calculate the start address of a vector. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Clarify terminology in vec_reg_offset()David Hildenbrand1-5/+6
We will use s390x speak "Element Size" (es) for MO_8 == 0, MO_16 == 1 ... Simple rename of variables. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Simplify disassembler operands initializationDavid Hildenbrand1-7/+1
Let's simplify initialization to 0. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: RXE has an optional M3 fieldDavid Hildenbrand1-1/+1
Will be needed, so add it to the format description. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/vfio-ap: document hot plug/unplug of vfio-ap deviceTony Krowiak1-5/+56
Let's update the vfio-ap.txt document to include the hot plug/unplug support. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Message-Id: <1550519397-25359-3-git-send-email-akrowiak@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/vfio-ap: Implement hot plug/unplug of vfio-ap deviceTony Krowiak2-2/+12
Introduces hot plug/unplug support for the vfio-ap device. To hot plug a vfio-ap device using the QEMU device_add command: (qemu) device_add vfio-ap,sysfsdev=$path-to-mdev Where $path-to-mdev is the absolute path to the mediated matrix device to which AP resources to be used by the guest have been assigned. A vfio-ap device can be hot plugged only if: 1. A vfio-ap device has not been attached to the virtual machine's ap-bus via the QEMU command line or a prior hot plug action. 2. The guest was started with the CPU model feature for AP enabled (e.g., -cpu host,ap=on) To hot unplug a vfio-ap device using the QEMU device_del command: (qemu) device_del vfio-ap,sysfsdev=$path-to-mdev Where $path-to-mdev is the absolute path to the mediated matrix device specified when the vfio-ap device was attached to the virtual machine's ap-bus. A vfio-ap device can be hot unplugged only if: 1. A vfio-ap device has been attached to the virtual machine's ap-bus via the QEMU command line or a prior hot plug action. 2. The guest was started with the CPU model feature for AP enabled (e.g., -cpu host,ap=on) Please note that a hot plug handler is not necessary for the vfio-ap device because the AP matrix configuration for the guest is performed by the kernel device driver when the vfio-ap device is realized. The vfio-ap device represents a VFIO mediated device created in the host sysfs for use by a guest. The mdev device is configured with an AP matrix (i.e., adapters and domains) via its sysfs attribute interfaces prior to starting the guest or plugging a vfio-ap device in. When the device is realized, a file descriptor is opened on the mdev device which results in a callback to the vfio_ap kernel device driver. The device driver then configures the AP matrix in the guest's SIE state description from the AP matrix assigned via the mdev device's sysfs interfaces. The AP devices will be created for the guest when the AP bus running on the guest subsequently performs its periodic scan for AP devices. The qdev_simple_device_unplug_cb() callback function is used for the same reaons; namely, the vfio_ap kernel device driver will perform the AP resource de-configuration for the guest when the vfio-ap device is unplugged. When the vfio-ap device is unrealized, the mdev device file descriptor is closed which results in a callback to the vfio_ap kernel device driver. The device driver then clears the AP matrix configuration in the guest's SIE state description and resets all of the affected queues. The AP devices created for the guest will be removed when the AP bus running on the guest subsequently performs its periodic scan and finds there are no longer any AP resources assigned to the guest. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Message-Id: <1550519397-25359-2-git-send-email-akrowiak@linux.ibm.com> [CH: adapt to changed qbus_set_hotplug_handler() signature] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Save vregs to extended mchk save areaDavid Hildenbrand2-3/+47
If we have vector registers and the designation is not zero, we have to try to write the vector registers. If the designation is zero or if storing fails, we must not indicate validity. s390_build_validity_mcic() automatically already sets validity if the vector instruction facility is installed. As long as we don't support the guarded-storage facility, the alignment and size of the area is always 1024 bytes. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190222081153.14206-4-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x: use a QEMU-style typedef + name for SIGP save area structDavid Hildenbrand1-4/+4
Convert this to QEMU style. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190222081153.14206-3-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUSDavid Hildenbrand1-10/+21
As we will support vector instructions soon, and vector registers are stored in 64bit host chunks, let's use cpu_to_be64. Same applies to the guarded storage control block. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190222081153.14206-2-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-28xen-block: stop leaking memory in xen_block_drive_create()Paul Durrant1-7/+9
The locally allocated QDict-s need to be freed. ('file_layer' will be freed implicitly since it is added as an object to 'driver_layer'). Spotted by Coverity: CID 1398649 While in the neighbourhood free 'driver' and 'filename' as soon as they are added to the QDicts. Freeing after the 'done' label doesn't make that much sense as, if the error path jumps to that label, the values would be NULL anyway. This patch also makes that more obvious by taking the error path if 'params' is NULL and then asserting that both driver and filename are non-NULL in the normal path. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Message-Id: <20190219163440.15702-1-paul.durrant@citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2019-02-28xen-block: report error condition from vbd_name_to_disk()Paul Durrant1-6/+15
The function needs to make sure it is passed a valid disk name. This is easily done by making sure that the parsing loop results in a non-zero value. Spotted by Coverity: CID 1398640 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190215162533.19475-4-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2019-02-28xen-block: remove redundant assignmentPaul Durrant1-2/+1
The assignment to 'p' is unnecessary as the code will either goto 'invalid' or p will get overwritten. Spotted by Coverity: CID 1398638 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190215162533.19475-3-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2019-02-28dataplane/xen-block: remove dead codePaul Durrant1-4/+1
The if() statement is clearly bogus (dead code which should have been cleaned up when grant mapping was removed). Spotted by Coverity: CID 1398635 While in the neighbourhood, add a missing 'fall through' annotation. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190215162533.19475-2-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2019-02-28tests/tcg/xtensa: add FPU2000 coprocessor testsMax Filippov2-0/+28
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add FP1 group testsMax Filippov2-0/+142
Test comparisons and conditional move operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add FP0 group conversion testsMax Filippov2-0/+305
Test conversions for normal, NaN and Inf arguments. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add FP0 group arithmetic testsMax Filippov3-0/+191
Test arithmetic operations for normal, NaN and Inf arguments. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add LSCI/LSCX group testsMax Filippov2-0/+123
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add test for FLIXMax Filippov2-0/+61
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize MMU-related testsMax Filippov2-0/+8
Make MMU-related tests conditional on the presence of MMUv2 option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize windowed register testsMax Filippov1-9/+23
Make windowed register tests conditional on the presence of this option. Fix tests to work correctly for both 32 and 64 physical registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize and fix s32c1i testsMax Filippov1-0/+12
Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: fix SR tests for big endian configsMax Filippov1-4/+16
SR tests generate instructions that the assembler does not recognize and thus must take care about configuration endianness. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize and expand SR testsMax Filippov1-0/+133
Make tests for specific special registers conditional on the presence of the options that add these registers and test that the registers are not accessible otherwise. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize timer/CCOUNT testsMax Filippov1-4/+44
Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize interrupt testsMax Filippov2-18/+73
Make interrupt tests conditional on the presence of interrupt option and on the presence of level-1 and high level software interrupts. Don't use hard-coded interrupt level for the high level interrupt tests, choose high level software IRQ and use its configured level. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add straightforward conditionalsMax Filippov12-0/+52
Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize cache option testsMax Filippov1-12/+50
Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize debug option testsMax Filippov2-9/+21
Make debug tests conditional on the presence of the debug option in the config and tests that depend on the presence/number of instruction or data breakpoint registers on the corresponding definitions. Use configured debug interrupt level instead of the hardcoded value to set up IRQ handler and access debug EPC register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: enable boolean testsMax Filippov2-1/+5
Uncomment test_boolean in the test makefile. Make actual tests code conditional on the presence of boolean option in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: fix endianness issues in test_bMax Filippov1-8/+32
Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that accept little-endian bit number and produce correct immediate for both little and big endian configurations. Choose value loaded into register for bbc/bbs opcodes based on configuration endianness. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: don't use optional opcodes in generic codeMax Filippov1-4/+7
Don't use 'loop' opcode in generic testsuite completion code, only use core opcodes to make it work with any configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: support configs with LITBASEMax Filippov1-0/+1
Configurations with LITBASE register may use absolute literals by default. Pass --no-absolute-literals option to assembler to use PC-relative literals instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: support configurations w/o vecbaseMax Filippov3-22/+63
Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>