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2018-05-04spapr: Clean up LPCR updates from hypercallsDavid Gibson1-30/+20
There are several places in spapr_hcall.c where we need to update the LPCR value on all CPUs. We do this with the set_spr() helper. That's not really correct because this directly sets the SPR value, without going through the ppc_store_lpcr() helper which may need to update state based on the LPCR change. In fact, set_spr() is only ever used for the LPCR, so replace it with an explicit LPCR updated which uses the right low-level helper. While we're there, move the CPU_FOREACH() which was in every one of the callers into the new helper: set_all_lpcrs(). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org>
2018-05-04spapr: Make a helper to set up cpu entry point stateDavid Gibson4-7/+15
Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify make a helper which sets up the common entry state for both boot and secondary cpu threads. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
2018-05-04spapr: Remove unhelpful helpers from rtas_start_cpu()David Gibson1-24/+14
rtas_start_cpu() calls spapr_cpu_update_tb_offset() and spapr_cpu_set_endianness() to initialize certain things in the new cpu's state. This is the only caller of those helpers, and they're each only a few lines long, so we might as well just fold them into the caller. In addition, those helpers initialize state on the new cpu to match that of the first cpu. That will generally work, but might be at least logically incorrect if the first cpu has been set offline by the guest. So, instead base the state on that of the cpu invoking the RTAS call, which is obviously active already. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
2018-05-04spapr: Clean up rtas_start_cpu() & rtas_stop_self()David Gibson1-34/+32
This makes several minor cleanups to these functions: * Follow usual convention of an early exit on error, rather than having most of the body in an if * Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the RTAS call is invoked, newcpu is the cpu which we're starting * Use cpu_synchronize_state() instead of kvm_cpu_synchronize_state() directly * Remove pointless comment describing what cpu_synchronize_state() does * Use ppc_store_lpcr() instead of directly writing the register field Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
2018-05-04target/ppc: Add ppc_store_lpcr() helperDavid Gibson3-11/+13
There are some fields in the cpu state which need to be updated when the LPCR register is changed, which is done by ppc_hash64_update_rmls() and ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to call them afterwards to make sure the state is up to date. That's easy to get wrong. The normal way of dealing with sitautions like that is to use a helper which both updates the basic register value and the derived state. So, do that. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
2018-05-04spapr: Remove support for explicitly allocated RMAsDavid Gibson3-90/+19
Current POWER cpus allow for a VRMA, a special mapping which describes a guest's view of memory when in real mode (MMU off, from the guest's point of view). Older cpus didn't have that which meant that to support a guest a special host-contiguous region of memory was needed to give the guest its Real Mode Area (RMA). KVM used to provide special calls to allocate a contiguous RMA for those cases. This was useful in the early days of KVM on Power to allow it to be tested on PowerPC 970 chips as used in Macintosh G5 machines. Now, those machines are so old as to be almost irrelevant. The normal qemu deprecation process would require this to be marked deprecated then removed in 2 releases. However, this can only be used with corresponding support in the host kernel - which was dropped years ago (in c17b98cf "KVM: PPC: Book3S HV: Remove code for PPC970 processors" of 2014-12-03 to be precise). Therefore it should be ok to drop this immediately. Just to be clear this only affects *KVM HV* guests with PowerPC 970, and those already require an ancient host kernel. TCG and KVM PR guests with PowerPC 970 should still work. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Thomas Huth <thuth@redhat.com>
2018-05-04target/ppc: add basic support for PTCR on POWER9Cédric Le Goater7-0/+71
The Partition Table Control Register (PTCR) is a hypervisor privileged SPR. It contains the host real address of the Partition Table and its size. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-05-04target/ppc: return a nil HPT base address on sPAPR machinesCédric Le Goater1-0/+3
commit e57ca75ce3b2 ("target/ppc: Manage external HPT via virtual hypervisor") exported a set of methods to manipulate the HPT from the core hash MMU. But SPR_SDR1 is still used under some circumstances to get the base address of the HPT, which is incorrect for the sPAPR machines. Only the logging should be impacted. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-05-029p: add trace event for v9fs_setattr()Greg Kurz2-0/+7
Don't print the tv_nsec part of atime and mtime, to stay below the 10 argument limit of trace events. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-05-01tcg: workaround branch instruction overflow in tcg_out_qemu_ld/stLaurent Vivier3-6/+6
ppc64 uses a BC instruction to call the tcg_out_qemu_ld/st slow path. BC instruction uses a relative address encoded on 14 bits. The slow path functions are added at the end of the generated instructions buffer, in the reverse order of the callers. So more we have slow path functions more the distance between the caller (BC) and the function increases. This patch changes the behavior to generate the functions in the same order of the callers. Cc: qemu-stable@nongnu.org Fixes: 15fa08f845 ("tcg: Dynamically allocate TCGOps") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20180429235840.16659-1-lvivier@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-01tcg: Improve TCGv_ptr supportRichard Henderson4-94/+130
Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros. Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr, tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32. Use inlines instead of macros where possible. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-01tcg: Allow wider vectors for cmp and mulRichard Henderson1-4/+4
In db432672, we allow wide inputs for operations such as add. However, in 212be173 and 3774030a we didn't do the same for compare and multiply. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-01tcg/arm: Fix memory barrier encodingHenry Wertz1-2/+2
I found with qemu 2.11.x or newer that I would get an illegal instruction error running some Intel binaries on my ARM chromebook. On investigation, I found it was quitting on memory barriers. qemu instruction: mb $0x31 was translating as: 0x604050cc: 5bf07ff5 blpl #0x600250a8 After patch it gives: 0x604050cc: f57ff05b dmb ish In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be correct based on online docs, but due to some endian-related shenanigans it had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier for ARMv6) also should be byte swapped (and this patch does so). I have not checked for correctness of aarch64's barrier instruction. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Henry Wertz <hwertz10@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-01tcg: Document INDEX_mul[us]h_*Richard Henderson1-0/+8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-01hw/m68k/mcf5208: Fix trivial typo in board descriptionThomas Huth1-1/+1
It's the MCF5208 evaluation board, not the MCF5206 eval board. Signed-off-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180429094002.3293c9de@thl530.multi.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-05-01m68k: remove dead code (Coverity CID1390617)Laurent Vivier1-29/+14
floatx80_sin() and floatx80_cos() are derived from one sincos() function. They have both unused code coming from their common origin. Remove it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180430170156.1860-2-laurent@vivier.eu>
2018-05-01m68k: Fix floatx80_lognp1 (Coverity CID1390587)Laurent Vivier1-1/+2
return the result of packFloatx80() instead of dropping it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180430170156.1860-1-laurent@vivier.eu>
2018-04-30target-microblaze: mmu: Make the TLBX MISS bit read-onlyEdgar E. Iglesias1-0/+4
Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: mmu: Make TLBSX write-onlyEdgar E. Iglesias1-1/+4
Make TLBSX write-only and guest-error log reads from it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Don't clobber the IMM reg for ld/st reversedEdgar E. Iglesias1-2/+0
Do not clobber the IMM register on reversed load/stores. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Fix trap checks for FPU insnsEdgar E. Iglesias1-1/+1
Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Respect MSR.PVR as read-onlyEdgar E. Iglesias1-1/+1
Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30m68k: fix subx mem, mem instructionPavel Dovgalyuk1-2/+2
This patch fixes decrement of the pointers for subx mem, mem instructions. Without the patch pointers are decremented by OS_* constant value instead of retrieving the corresponding data size and using it as a decrement. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180418064152.24606.71975.stgit@pasha-VirtualBox> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-04-30linux-user: Add ARM get_tls syscall supportChristophe Lyon2-0/+4
Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180416091845.7315-1-christophe.lyon@st.com> [lv: moved the change to linux-user/arm/cpu_loop.c] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-04-30linux-user: move xtensa cpu loop to xtensa directoryLaurent Vivier2-250/+241
No code change, only move code from main.c to xtensa/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-20-laurent@vivier.eu>
2018-04-30linux-user: move hppa cpu loop to hppa directoryLaurent Vivier2-193/+186
No code change, only move code from main.c to hppa/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-19-laurent@vivier.eu>
2018-04-30linux-user: move riscv cpu loop to riscv directoryLaurent Vivier2-100/+93
No code change, only move code from main.c to riscv/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-18-laurent@vivier.eu>
2018-04-30linux-user: move tilegx cpu loop to tilegx directoryLaurent Vivier2-267/+260
No code change, only move code from main.c to tilegx/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-17-laurent@vivier.eu>
2018-04-30linux-user: move s390x cpu loop to s390x directoryLaurent Vivier2-146/+139
No code change, only move code from main.c to s390x/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-16-laurent@vivier.eu>
2018-04-30linux-user: move alpha cpu loop to alpha directoryLaurent Vivier2-204/+199
No code change, only move code from main.c to alpha/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-15-laurent@vivier.eu>
2018-04-30linux-user: move m68k cpu loop to m68k directoryLaurent Vivier2-149/+145
No code change, only move code from main.c to m68k/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-14-laurent@vivier.eu>
2018-04-30linux-user: move microblaze cpu loop to microblaze directoryLaurent Vivier2-155/+150
No code change, only move code from main.c to microblaze/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-13-laurent@vivier.eu>
2018-04-30linux-user: move cris cpu loop to cris directoryLaurent Vivier2-90/+89
No code change, only move code from main.c to cris/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-12-laurent@vivier.eu>
2018-04-30linux-user: move sh4 cpu loop to sh4 directoryLaurent Vivier2-90/+85
No code change, only move code from main.c to sh4/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-11-laurent@vivier.eu>
2018-04-30linux-user: move openrisc cpu loop to openrisc directoryLaurent Vivier2-96/+89
No code change, only move code from main.c to openrisc/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-10-laurent@vivier.eu>
2018-04-30linux-user: move nios2 cpu loop to nios2 directoryLaurent Vivier2-133/+126
No code change, only move code from main.c to nios2/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-9-laurent@vivier.eu>
2018-04-30linux-user: move mips/mips64 cpu loop to mips directoryLaurent Vivier3-732/+724
No code change, only move code from main.c to mips/cpu_loop.c. Include mips/cpu_loop.c in mips64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-8-laurent@vivier.eu>
2018-04-30linux-user: move ppc/ppc64 cpu loop to ppc directoryLaurent Vivier2-559/+554
No code change, only move code from main.c to ppc/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-7-laurent@vivier.eu>
2018-04-30linux-user: move sparc/sparc64 cpu loop to sparc directoryLaurent Vivier3-294/+282
No code change, only move code from main.c to sparc/cpu_loop.c. Include sparc/cpu_loop.c in sparc64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180411185651.21351-6-laurent@vivier.eu>
2018-04-30linux-user: move arm cpu loop to arm directoryLaurent Vivier2-431/+432
No code change, only move code from main.c to arm/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-5-laurent@vivier.eu>
2018-04-30linux-user: move aarch64 cpu loop to aarch64 directoryLaurent Vivier2-107/+158
No code change, only move code from main.c to aarch64/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-4-laurent@vivier.eu>
2018-04-30linux-user: move i386/x86_64 cpu loop to i386 directoryLaurent Vivier3-354/+345
No code change, only move code from main.c to i386/cpu_loop.c. Include i386/cpu_loop.c in x86_64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-3-laurent@vivier.eu>
2018-04-30linux-user: create a dummy per arch cpu_loop.cLaurent Vivier24-15/+588
Create a cpu_loop-common.h for future use by these new files and use it in the existing main.c Introduce target_cpu_copy_regs(): declare the function in cpu_loop-common.h and an empty function for each target, to move all the cpu_loop prologues to this function. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-2-laurent@vivier.eu>
2018-04-30linux-user: define TARGET_ARCH_HAS_SETUP_FRAMELaurent Vivier23-110/+28
Instead of calling setup_frame() conditionally to a list of known targets, define TARGET_ARCH_HAS_SETUP_FRAME if the target provides the function and call it only if the macro is defined. Move declarations of setup_frame() and setup_rt_frame() to linux-user/signal-common.h Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-21-laurent@vivier.eu>
2018-04-30linux-user: move ppc/ppc64 signal.c parts to ppc directoryLaurent Vivier3-670/+678
No code change, only move code from signal.c to ppc/signal.c, except adding includes and exporting setup_frame() and setup_rt_frame(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-20-laurent@vivier.eu>
2018-04-30linux-user: move mips/mips64 signal.c parts to mips directoryLaurent Vivier5-382/+396
No code change, only move code from signal.c to mips/signal.c, except adding includes and exporting setup_frame() and setup_rt_frame(). mips64/signal.c includes mips/signal.c Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-19-laurent@vivier.eu>
2018-04-30linux-user: move sparc/sparc64 signal.c parts to sparc directoryLaurent Vivier5-605/+619
No code change, only move code from signal.c to sparc/signal.c, except adding includes and exporting setup_frame() and setup_rt_frame(). sparc64/signal.c includes sparc/signal.c Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-18-laurent@vivier.eu>
2018-04-30linux-user: move i386/x86_64 signal.c parts to i386 directoryLaurent Vivier5-581/+595
No code change, only move code from signal.c to i386/signal.c, except adding includes and exporting setup_frame() and setup_rt_frame(). x86_64/signal.c includes i386/signal.c Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-17-laurent@vivier.eu>
2018-04-30linux-user: move xtensa signal.c parts to xtensa directoryLaurent Vivier3-247/+253
No code change, only move code from signal.c to xtensa/signal.c, except adding includes and exporting setup_rt_frame(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-16-laurent@vivier.eu>
2018-04-30linux-user: move hppa signal.c parts to hppa directoryLaurent Vivier3-189/+195
No code change, only move code from signal.c to hppa/signal.c, except adding includes and exporting setup_rt_frame(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180424192635.6027-15-laurent@vivier.eu>