| Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-09-02 | Revert "target/i386: Cleanup and use the EPYC mode topology functions" | Babu Moger | 1 | -34/+127 |
| 2020-09-02 | Revert "hw/i386: Introduce apicid functions inside X86MachineState" | Babu Moger | 2 | -14/+0 |
| 2020-09-02 | Revert "i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition" | Babu Moger | 2 | -17/+0 |
| 2020-09-02 | Revert "hw/i386: Move arch_id decode inside x86_cpus_init" | Babu Moger | 2 | -33/+10 |
| 2020-09-02 | Revert "target/i386: Enable new apic id encoding for EPYC based cpus models" | Babu Moger | 1 | -2/+0 |
| 2020-09-02 | Revert "i386: Fix pkg_id offset for EPYC cpu models" | Babu Moger | 3 | -7/+4 |
| 2020-09-02 | tls-cipher-suites: Correct instance_size | Eduardo Habkost | 1 | -1/+1 |
| 2020-09-02 | hda-audio: Set instance_size at base class | Eduardo Habkost | 1 | -3/+1 |
| 2020-09-02 | rx: Move typedef RXCPU to cpu-qom.h | Eduardo Habkost | 2 | -1/+1 |
| 2020-09-02 | rx: Rename QOM type check macros | Eduardo Habkost | 6 | -17/+17 |
| 2020-09-02 | arm: Fix typo in AARCH64_CPU_GET_CLASS definition | Eduardo Habkost | 1 | -1/+1 |
| 2020-09-02 | rdma: Rename INTERFACE_RDMA_PROVIDER_CLASS macro | Eduardo Habkost | 2 | -2/+2 |
| 2020-09-02 | x86-iommu: Rename QOM type macros | Eduardo Habkost | 5 | -6/+6 |
| 2020-09-02 | mos6522: Rename QOM macros | Eduardo Habkost | 5 | -19/+19 |
| 2020-09-02 | imx_ccm: Rename IMX_GET_CLASS macro | Eduardo Habkost | 2 | -2/+2 |
| 2020-09-01 | hw/arm/sbsa-ref : Add embedded controller in secure memory | Graeme Gregory | 1 | -0/+14 |
| 2020-09-01 | hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref | Graeme Gregory | 2 | -0/+100 |
| 2020-09-01 | hw/arm/sbsa-ref: add "reg" property to DT cpu nodes | Leif Lindholm | 1 | -6/+23 |
| 2020-09-01 | target/arm: Enable FP16 in '-cpu max' | Peter Maydell | 2 | -7/+6 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS | Peter Maydell | 1 | -55/+55 |
| 2020-09-01 | target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations | Peter Maydell | 2 | -5/+32 |
| 2020-09-01 | target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations | Peter Maydell | 1 | -4/+8 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VRINTX | Peter Maydell | 3 | -42/+9 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode | Peter Maydell | 4 | -79/+30 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VCVT with rounding modes | Peter Maydell | 3 | -67/+66 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VCVT fixed-point | Peter Maydell | 4 | -1/+21 |
| 2020-09-01 | target/arm: Convert Neon VCVT fixed-point to gvec | Peter Maydell | 3 | -17/+43 |
| 2020-09-01 | target/arm: Implement fp16 for Neon float-integer VCVT | Peter Maydell | 3 | -11/+42 |
| 2020-09-01 | target/arm: Implement fp16 for Neon pairwise fp ops | Peter Maydell | 3 | -26/+68 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VRSQRTS | Peter Maydell | 4 | -36/+34 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VRECPS | Peter Maydell | 4 | -34/+35 |
| 2020-09-01 | target/arm: Implement fp16 for Neon fp compare-vs-0 | Peter Maydell | 3 | -28/+45 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VFMA, VMFS | Peter Maydell | 3 | -91/+40 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VMLA, VMLS operations | Peter Maydell | 3 | -31/+50 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VMAXNM, VMINNM | Peter Maydell | 3 | -8/+27 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VMAX, VMIN | Peter Maydell | 3 | -3/+14 |
| 2020-09-01 | target/arm: Implement fp16 for VACGE, VACGT | Peter Maydell | 3 | -2/+34 |
| 2020-09-01 | target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons | Peter Maydell | 3 | -3/+56 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VABS, VNEG of floats | Peter Maydell | 1 | -6/+28 |
| 2020-09-01 | target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec | Peter Maydell | 1 | -2/+29 |
| 2020-09-01 | target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL | Peter Maydell | 3 | -17/+26 |
| 2020-09-01 | target/arm: Implement VFP fp16 VMOV between gp and halfprec registers | Peter Maydell | 2 | -0/+35 |
| 2020-09-01 | target/arm: Implement new VFP fp16 insn VMOVX | Peter Maydell | 2 | -0/+28 |
| 2020-09-01 | target/arm: Implement new VFP fp16 insn VINS | Peter Maydell | 2 | -0/+31 |
| 2020-09-01 | target/arm: Implement VFP fp16 VRINT* | Peter Maydell | 5 | -8/+122 |
| 2020-09-01 | target/arm: Implement VFP fp16 VSEL | Peter Maydell | 2 | -6/+16 |
| 2020-09-01 | target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode | Peter Maydell | 2 | -10/+28 |
| 2020-09-01 | target/arm: Implement VFP fp16 VCVT between float and fixed-point | Peter Maydell | 2 | -0/+61 |
| 2020-09-01 | target/arm: Use macros instead of open-coding fp16 conversion helpers | Peter Maydell | 2 | -80/+12 |
| 2020-09-01 | target/arm: Make VFP_CONV_FIX macros take separate float type and float size | Peter Maydell | 1 | -23/+23 |