focaccia-qemu - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Files	Lines
2021-05-14	exec/gen-icount.h: Add missing "exec/exec-all.h" include	Philippe Mathieu-Daudé	1	-0/+1
2021-05-14	MAINTAINERS: Add include/exec/gen-icount.h to 'Main Loop' section	Philippe Mathieu-Daudé	1	-0/+1
2021-05-12	Drop the deprecated unicore32 target	Markus Armbruster	42	-4582/+16
2021-05-12	Drop the deprecated lm32 target	Markus Armbruster	150	-12234/+17
2021-05-12	block: Drop the sheepdog block driver	Markus Armbruster	17	-3593/+14
2021-05-12	Remove the deprecated moxie target	Thomas Huth	38	-1987/+13
2021-05-12	monitor/qmp: fix race on CHR_EVENT_CLOSED without OOB	Stefan Reiter	1	-18/+22
2021-05-12	coverity-scan: list components, move model to scripts/coverity-scan	Paolo Bonzini	2	-0/+154
2021-05-12	configure: fix detection of gdbus-codegen	Paolo Bonzini	1	-1/+3
2021-05-12	qemu-option: support accept-any QemuOptsList in qemu_opts_absorb_qdict	Paolo Bonzini	1	-1/+2
2021-05-11	hw/block/pflash_cfi02: Do not create aliases when not necessary	Philippe Mathieu-Daudé	1	-2/+6
2021-05-11	hw/block/pflash_cfi02: Set romd mode in pflash_cfi02_realize()	Philippe Mathieu-Daudé	1	-1/+1
2021-05-11	target/riscv: Fix the RV64H decode comment	Alistair Francis	1	-1/+1
2021-05-11	target/riscv: Consolidate RV32/64 16-bit instructions	Alistair Francis	5	-72/+39
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis	14	-150/+166
2021-05-11	target/riscv: Remove an unused CASE_OP_32_64 macro	Alistair Francis	1	-6/+0
2021-05-11	target/riscv: Remove the unused HSTATUS_WPRI macro	Alistair Francis	1	-6/+0
2021-05-11	target/riscv: Remove the hardcoded SATP_MODE macro	Alistair Francis	4	-28/+56
2021-05-11	target/riscv: Remove the hardcoded MSTATUS_SD macro	Alistair Francis	3	-14/+27
2021-05-11	target/riscv: Remove the hardcoded HGATP_MODE macro	Alistair Francis	2	-20/+15
2021-05-11	target/riscv: Remove the hardcoded SSTATUS_SD macro	Alistair Francis	2	-7/+8
2021-05-11	target/riscv: Remove the hardcoded RVXLEN macro	Alistair Francis	2	-7/+5
2021-05-11	target/riscv: fix a typo with interrupt names	Emmanuel Blot	1	-1/+1
2021-05-11	fpu/softfloat: set invalid excp flag for RISC-V muladd instructions	Frank Chang	1	-0/+6
2021-05-11	hw/riscv: Fix OT IBEX reset vector	Alexander Wagner	1	-1/+1
2021-05-11	target/riscv: fix exception index on instruction access fault	Emmanuel Blot	1	-1/+3
2021-05-11	target/riscv: fix vrgather macro index variable type bug	Frank Chang	1	-2/+4
2021-05-11	target/riscv: Add ePMP support for the Ibex CPU	Alistair Francis	1	-0/+1
2021-05-11	target/riscv/pmp: Remove outdated comment	Alistair Francis	1	-4/+0
2021-05-11	target/riscv: Add a config option for ePMP	Hou Weiying	2	-0/+11
2021-05-11	target/riscv: Implementation of enhanced PMP (ePMP)	Hou Weiying	1	-8/+146
2021-05-11	target/riscv: Add ePMP CSR access functions	Hou Weiying	5	-0/+76
2021-05-11	target/riscv: Add the ePMP feature	Alistair Francis	1	-0/+1
2021-05-11	target/riscv: Define ePMP mseccfg	Hou Weiying	1	-0/+3
2021-05-11	target/riscv: Fix the PMP is locked check when using TOR	Alistair Francis	1	-10/+16
2021-05-11	docs: Add documentation for shakti_c machine	Vijai Kumar K	2	-0/+83
2021-05-11	target/riscv: Fixup saturate subtract function	LIU Zhiwei	1	-4/+4
2021-05-11	riscv: don't look at SUM when accessing memory from a debugger context	Jade Fink	1	-8/+12
2021-05-11	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine	Alistair Francis	1	-0/+1
2021-05-11	hw/opentitan: Update the interrupt layout	Alistair Francis	3	-22/+22
2021-05-11	MAINTAINERS: Update the RISC-V CPU Maintainers	Alistair Francis	1	-3/+2
2021-05-11	target/riscv: Use RISCVException enum for CSR access	Alistair Francis	4	-36/+38
2021-05-11	target/riscv: Use the RISCVException enum for CSR operations	Alistair Francis	2	-261/+382
2021-05-11	target/riscv: Fix 32-bit HS mode access permissions	Alistair Francis	1	-1/+5
2021-05-11	target/riscv: Use the RISCVException enum for CSR predicates	Alistair Francis	2	-37/+46
2021-05-11	target/riscv: Convert the RISC-V exceptions to an enum	Alistair Francis	3	-24/+26
2021-05-11	hw/riscv: Connect Shakti UART to Shakti platform	Vijai Kumar K	2	-0/+10
2021-05-11	hw/char: Add Shakti UART emulation	Vijai Kumar K	5	-0/+266
2021-05-11	riscv: Add initial support for Shakti C machine	Vijai Kumar K	6	-0/+265
2021-05-11	target/riscv: Add Shakti C class CPU	Vijai Kumar K	2	-0/+2