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2025-09-30ui/spice: Fix abort on macOSMohamed Akram1-5/+1
The check is faulty because the thread variable was assigned in the main thread while the main loop runs in a different thread on macOS. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3070 Signed-off-by: Mohamed Akram <mohd.akram@outlook.com> Acked-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <C87205B9-DD8F-4E53-AB5B-C8BF82EF1D16@outlook.com>
2025-09-30gtk: Skip drawing if console surface is NULLWeifeng Liu2-8/+2
In gtk draw/render callbacks, add an early NULL check for the console surface and skip drawing if it's NULL. Otherwise, attempting to fetch its width and height crash. This change fixes Coverity CID 1610328. In practice, this case wouldn't happen at all because we always install a placeholder surface to the console when there is nothing to display. Resolves: Coverity CID 1610328 Signed-off-by: Weifeng Liu <weifeng.liu.z@gmail.com> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250714141758.10062-1-weifeng.liu.z@gmail.com>
2025-09-28target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear maskDenis Sergeev1-1/+1
In gen_mcrfs() the FPSCR nibble mask is computed as: `~((0xF << shift) & FP_EX_CLEAR_BITS)` Here, 0xF is of type int, so the left shift is performed in 32-bit signed arithmetic. For bfa=0 we get shift=28, and (0xF << 28) = 0xF0000000, which is not representable as a 32-bit signed int. Static analyzers flag this as a potential integer overflow. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Denis Sergeev <zeff@altlinux.org> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250915080118.29898-1-zeff@altlinux.org Message-ID: <20250915080118.29898-1-zeff@altlinux.org>
2025-09-28target/ppc: Deprecate Power8E and Power8NVLAditya Gupta2-4/+13
Power8E and Power8NVL variants are not of much use in QEMU now, and not being maintained either. Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit to be exact: commit c5424f683ee3 ("Remove support for POWER8 DD1") Deprecate the 8E and 8NVL variants. Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Anushree Mathur <anushree.mathur@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250607110412.2342511-3-adityag@linux.ibm.com Message-ID: <20250607110412.2342511-3-adityag@linux.ibm.com>
2025-09-28target/ppc: Introduce macro for deprecating PowerPC CPUsAditya Gupta2-2/+17
QEMU has a way to deprecate CPUs by setting the 'deprecation_note' in CPUClass. Currently PowerPC CPUs don't use this deprecation process. Introduce 'POWERPC_DEPRECATED_CPU' macro to deprecate particular PowerPC CPUs in future. With the change, QEMU will print a warning like below when the deprecated CPU/Chips are used (example output if power8nvl is deprecated): $ ./build/qemu-system-ppc64 -M powernv8 --cpu power8nvl -nographic qemu-system-ppc64: warning: CPU model power8nvl_v1.0-powerpc64-cpu is deprecated -- CPU is unmaintained. ... Also, print '(deprecated)' for deprecated CPUs in 'qemu-system-ppc64 --cpu ?' (example output if power8nvl is deprecated): $ ./build/qemu-system-ppc64 --cpu help ... power8e (alias for power8e_v2.1) power8nvl_v1.0 PVR 004c0100 (deprecated) power8nvl (alias for power8nvl_v1.0) power8_v2.0 PVR 004d0200 ... Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Anushree Mathur <anushree.mathur@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250607110412.2342511-2-adityag@linux.ibm.com Message-ID: <20250607110412.2342511-2-adityag@linux.ibm.com>
2025-09-28target/ppc: Move remaining floating-point move instructions to decodetree.Chinmay Rath3-40/+32
Move below instructions to decodetree specification: fcpsgn, fmrg{e, o}w : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-5-rathc@linux.ibm.com Message-ID: <20250619095840.369351-5-rathc@linux.ibm.com>
2025-09-28target/ppc: Move floating-point move instructions to decodetree.Chinmay Rath3-63/+28
Move below instructions to decodetree specification: f{mr, neg, abs, nabs} : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-4-rathc@linux.ibm.com Message-ID: <20250619095840.369351-4-rathc@linux.ibm.com>
2025-09-28target/ppc: Move floating-point compare instructions to decodetree.Chinmay Rath5-38/+22
Move below instructions to decodetree specification : fcmp{u, o} : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-3-rathc@linux.ibm.com Message-ID: <20250619095840.369351-3-rathc@linux.ibm.com>
2025-09-28target/ppc: Move floating-point rounding and conversion instructions to ↵Chinmay Rath5-114/+98
decodetree. Move below instructions to decodetree specification : fr{sp, in, iz, im}[s][.], fcti{w, d}[u, z, uz][s][.], fcfid[s, u, us][s][.] : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250619095840.369351-2-rathc@linux.ibm.com Message-ID: <20250619095840.369351-2-rathc@linux.ibm.com>
2025-09-28ppc/xive2: Fix integer overflow warning in xive2_redistribute()Gautam Menghani1-14/+31
Coverity reported an integer overflow warning in xive2_redistribute() where the code does a left shift operation "0xffffffff << crowd". Fix the warning by using a 64 byte integer type. Also refactor the calculation into dedicated routines. Resolves: Coverity CID 1612608 Fixes: 555e446019f5 ("ppc/xive2: Support redistribution of group interrupts") Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Gautam Menghani <gautam@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250811074912.162774-1-gautam@linux.ibm.com Message-ID: <20250811074912.162774-1-gautam@linux.ibm.com>
2025-09-28ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not providedHarsh Prateek Bora1-4/+7
lrdr-capacity contains phys field which communicates the maximum address in bytes and therefore, the most memory that can be allocated to this partition. This is usually populated when maxmem is provided alongwith memory size on qemu command line. However since maxmem is an optional param, this leads to bits being set to 0 in absence of maxmem param. Fix this by initializing the respective bits as per total mem size in such case. Reported-by: Gaurav Batra <gbatra@us.ibm.com> Tested-by: David Christensen <drc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Link: https://lore.kernel.org/r/20250506042903.76250-1-harshpb@linux.ibm.com Message-ID: <20250506042903.76250-1-harshpb@linux.ibm.com>
2025-09-28hw/intc/xics: Add missing call to register vmstate_icp_serverFabian Vogt1-0/+2
An obsolete wrapper function with a workaround was removed entirely, without restoring the call it wrapped. Without this, the guest is stuck after savevm/loadvm. Fixes: 24ee9229fe31 ("ppc/spapr: remove deprecated machine pseries-2.9") Signed-off-by: Fabian Vogt <fvogt@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/6187781.lOV4Wx5bFT@fvogt-thinkpad Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Gautam Menghani <gautam@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250819223905.2247-2-farosas@suse.de Message-ID: <20250819223905.2247-2-farosas@suse.de>
2025-09-28tests/functional: Add test for IBM PPE42 instructionsGlenn Miles3-0/+81
Adds a functional test for the IBM PPE42 instructions which downloads a test image from a public github repo and then loads and executes the image. (see https://github.com/milesg-github/ppe42-tests for details) Test status is checked by periodically issuing 'info register' commands and checking the NIP value. If the NIP is 0xFFF80200 then the test successfully executed to completion. If the machine stops before the test completes or if a 90 second timeout is reached, then the test is marked as having failed. This test does not test any PowerPC instructions as it is expected that these instructions are well covered in other tests. Only instructions that are unique to the IBM PPE42 processor are tested. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-10-milesg@linux.ibm.com Message-ID: <20250925201758.652077-10-milesg@linux.ibm.com>
2025-09-28hw/ppc: Add a test machine for the IBM PPE42 CPUGlenn Miles4-0/+114
Adds a test machine for the IBM PPE42 processor, including a DEC, FIT, WDT and 512 KiB of ram. The purpose of this machine is only to provide a generic platform for testing instructions of the recently added PPE42 processor model which is used extensively in the IBM Power9, Power10 and future Power server processors. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-9-milesg@linux.ibm.com Message-ID: <20250925201758.652077-9-milesg@linux.ibm.com>
2025-09-28hw/ppc: Support for an IBM PPE42 CPU decrementerGlenn Miles2-1/+7
The IBM PPE42 processors support a 32-bit decrementer that can raise an external interrupt when DEC[0] transitions from a 0 to a -1 (a non-negative value to a negative value). It also continues decrementing even after this condition is met. The BookE timer is slightly different in that it raises an interrupt when the DEC value reaches 0 and stops decrementing at that point. Support a PPE42 version of the BookE timer by adding a new PPC_TIMER_PPE flag that has the timer code look for the transition from a non-negative value to a negative value and allows the value to continue decrementing. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-8-milesg@linux.ibm.com Message-ID: <20250925201758.652077-8-milesg@linux.ibm.com>
2025-09-28target/ppc: Add IBM PPE42 special instructionsGlenn Miles3-10/+694
Adds the following instructions exclusively for IBM PPE42 processors: LSKU LCXU STSKU STCXU LVD LVDU LVDX STVD STVDU STVDX SLVD SRVD CMPWBC CMPLWBC CMPWIBC BNBWI BNBW CLRBWIBC CLRWBC DCBQ RLDICL RLDICR RLDIMI A PPE42 GCC compiler is available here: https://github.com/open-power/ppe42-gcc For more information on the PPE42 processors please visit: https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-7-milesg@linux.ibm.com Message-ID: <20250925201758.652077-7-milesg@linux.ibm.com>
2025-09-28target/ppc: Support for IBM PPE42 MMUGlenn Miles1-0/+4
The IBM PPE42 processor only supports real mode addressing and does not distinguish between problem and supervisor states. It also uses the IR and DR MSR bits for other purposes. Therefore, add a check for PPE42 when we update hflags and cause it to ignore the IR and DR bits when calculating MMU indexes. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-6-milesg@linux.ibm.com Message-ID: <20250925201758.652077-6-milesg@linux.ibm.com>
2025-09-28target/ppc: Add IBM PPE42 exception modelGlenn Miles3-1/+213
Add support for the IBM PPE42 exception model including new exception vectors, exception priorities and setting of PPE42 SPRs for determining the cause of an exception. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-5-milesg@linux.ibm.com Message-ID: <20250925201758.652077-5-milesg@linux.ibm.com>
2025-09-28target/ppc: IBM PPE42 exception flags and regsGlenn Miles1-0/+27
Introduces flags and register definitions needed for the IBM PPE42 exception model. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-4-milesg@linux.ibm.com Message-ID: <20250925201758.652077-4-milesg@linux.ibm.com>
2025-09-28target/ppc: Add IBM PPE42 family of processorsGlenn Miles4-56/+205
Adds the IBM PPE42 family of 32-bit processors supporting the PPE42, PPE42X and PPE42XM processor versions. These processors are used as embedded processors in the IBM Power9, Power10 and Power12 processors for various tasks. It is basically a stripped down version of the IBM PowerPC 405 processor, with some added instructions for handling 64-bit loads and stores. For more information on the PPE 42 processor please visit: https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf Supports PPE42 SPR's (Including the MSR). Does not yet support exceptions, new PPE42 instructions and does not prevent access to some invalid instructions and registers (currently allows access to invalid GPR's and CR fields). Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-3-milesg@linux.ibm.com Message-ID: <20250925201758.652077-3-milesg@linux.ibm.com>
2025-09-28target/ppc: IBM PPE42 general regs and flagsGlenn Miles2-1/+52
Introduces general IBM PPE42 processor register definitions and flags. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-2-milesg@linux.ibm.com Message-ID: <20250925201758.652077-2-milesg@linux.ibm.com>
2025-09-28tests/powernv: Add PowerNV test for Power11Aditya Gupta1-0/+4
With all Power11 support in place, add Power11 PowerNV test. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-9-adityag@linux.ibm.com Message-ID: <20250925173049.891406-9-adityag@linux.ibm.com>
2025-09-28tests/powernv: Switch to buildroot images instead of op-buildAditya Gupta1-14/+16
As op-build images haven't been updated from long time (and may not get updated in future), use buildroot images provided by cedric [1]. Use existing nvme device being used in the test to mount the initrd. Also replace the check for "zImage loaded message" to skiboot's message when it starts the kernel: "Starting kernel at", since we are no longer using zImage from op-build This is required for newer processor tests such as Power11, as the op-build kernel image is old and doesn't support Power11. Power11 test has been added in a later patch. [1]: https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-2025.02 Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-8-adityag@linux.ibm.com Message-ID: <20250925173049.891406-8-adityag@linux.ibm.com>
2025-09-28ppc/pnv: Add ChipTOD model for Power11Aditya Gupta3-0/+76
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod code as the Power11 core is same as Power10 core. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-7-adityag@linux.ibm.com Message-ID: <20250925173049.891406-7-adityag@linux.ibm.com>
2025-09-28ppc/pnv: Add PHB5 PCIe Host bridge to Power11Aditya Gupta1-1/+56
Power11 also uses PHB5, same as Power10. Add Power11 PHBs with similar code as the corresponding Power10 implementation. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-6-adityag@linux.ibm.com Message-ID: <20250925173049.891406-6-adityag@linux.ibm.com>
2025-09-28ppc/pnv: Add XIVE2 controller to Power11Aditya Gupta2-1/+138
Add a XIVE2 controller to Power11 chip and machine. The controller has the same logic as Power10. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-5-adityag@linux.ibm.com Message-ID: <20250925173049.891406-5-adityag@linux.ibm.com>
2025-09-28ppc/pnv: Add PnvChipClass handler to get reference to interrupt controllerAditya Gupta3-2/+15
Existing code in XIVE2 assumes the chip to be a Power10 Chip. Instead add a handler to get reference to the interrupt controller (XIVE) for a given Power Chip. Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-4-adityag@linux.ibm.com Message-ID: <20250925173049.891406-4-adityag@linux.ibm.com>
2025-09-28ppc/pnv: Introduce Power11 PowerNV machineAditya Gupta2-4/+39
The Powernv11 machine doesn't have XIVE & PHBs as of now XIVE2 interface and PHB5 added in later patches to Powernv11 machine Also add mention of Power11 to powernv documentation Note: A difference from P10's and P11's machine_class_init is, in P11 different number of PHBs cannot be used on the command line, ie. the following line does NOT exist in pnv_machine_power11_class_init, which existed in case of Power10: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-3-adityag@linux.ibm.com Message-ID: <20250925173049.891406-3-adityag@linux.ibm.com>
2025-09-28ppc/pnv: Introduce Pnv11ChipAditya Gupta5-0/+418
Implement Pnv11Chip, currently without chiptod, xive and phb. Chiptod, XIVE, PHB are implemented in later patches. Since Power11 core is same as Power10, the implementation of Pnv11Chip is a duplicate of corresponding Pnv10Chip. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-2-adityag@linux.ibm.com Message-ID: <20250925173049.891406-2-adityag@linux.ibm.com>
2025-09-28hw/loongarch: Implement DINTC plug/unplug interfacesSong Gao2-0/+82
when cpu added, connect dintc irq to cpu INT_DMSI irq pin. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20250916122109.749813-12-gaosong@loongson.cn>
2025-09-28target/loongarch:Implement csrrd CSR_MSGIR registerSong Gao4-0/+28
implement the read-clear feature for CSR_MSGIR register. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20250916122109.749813-11-gaosong@loongson.cn>
2025-09-28target/loongarch: Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for msg interrupts.Song Gao1-2/+4
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for DINTC irq. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20250916122109.749813-10-gaosong@loongson.cn>
2025-09-28hw/loongarch: Implement dintc set irqSong Gao1-2/+30
Implement dintc set irq and update CSR_MSGIS. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20250916122109.749813-9-gaosong@loongson.cn>
2025-09-28hw/loongarch: Implement dintc realize and unrealizeSong Gao2-2/+24
Implement th DINTC realize and unrealize. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-8-gaosong@loongson.cn>
2025-09-28hw/loongarch: DINTC add a MemoryRegionSong Gao5-1/+65
the DINTC use [2fe00000-2ff00000) Memory. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-7-gaosong@loongson.cn>
2025-09-28target/loongarch: add msg interrupt CSR registersSong Gao3-2/+37
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20250916122109.749813-6-gaosong@loongson.cn>
2025-09-28loongarch: add a direct interrupt controller deviceSong Gao5-0/+108
Add Loongarch direct interrupt controller device base Definition. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-5-gaosong@loongson.cn>
2025-09-28hw/loongarch: add misc register support dmsiSong Gao1-0/+11
Add feature register and misc register for dmsi feature checking and setting Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-4-gaosong@loongson.cn>
2025-09-28hw/loongarch: add virt feature dmsi supportSong Gao4-0/+94
dmsi feature is added in LoongArchVirtMachinState, and it is used to check whether virt machine supports the directy Message-Interrupts. and by default set dmsi with ON_OFF_AUTO_AUTO. LoongArchVirtMachineState adds misc_feature and misc_status for misc features and status. and set the default dintc feature bit. Msgint feature is added in LoongArchCPU, and it is used to check whether th cpu supports the Message-Interrupts and by default set mesgint with ON_OFF_AUTO_AUTO. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-3-gaosong@loongson.cn>
2025-09-28target/loongarch: move some machine define to virt.hSong Gao2-21/+19
move some machine define to virt.h Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-2-gaosong@loongson.cn>
2025-09-28target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()Bibo Mao1-2/+1
With function helper_invtlb_page_asid(), only one TLB entry in LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not necessary to flush all QEMU TLB, only flush address range specified LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called so that only QEMU TLB entry with specified address range is flushed. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-28target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()Bibo Mao1-2/+1
With function helper_invtlb_page_asid_or_g(), only one TLB entry in LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not necessary to flush all QEMU TLB, only flush address range specified LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called so that only QEMU TLB entry with specified address range is flushed. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-28target/loongarch: Invalid tlb entry in invalidate_tlb()Bibo Mao1-1/+1
Invalid tlb entry in function invalidate_tlb(), and its usage is simple and easy to use. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-09-28target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asidBibo Mao1-23/+13
With function helper_invtlb_page_asid(), currently it is to search TLB entry one by one. Instead STLB can be searched at first with hash method, and then search MTLB with one by one method Here common API loongarch_tlb_search_cb() is used in function helper_invtlb_page_asid() Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-28target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_gBibo Mao1-23/+8
With function helper_invtlb_page_asid_or_g(), currently it is to search TLB entry one by one. Instead STLB can be searched at first with hash method, and then search MTLB with one by one method. Here common API loongarch_tlb_search_cb() is used in function helper_invtlb_page_asid_or_g(). Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-28target/loongarch: Change return value type with loongarch_tlb_search_cb()Bibo Mao1-8/+14
With function loongarch_tlb_search_cb(), change return value type from bool type to pointer LoongArchTLB *, the pointer type can be use directly in future. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-09-28target/loongarch: Add common API loongarch_tlb_search_cb()Bibo Mao1-6/+14
Common API loongarch_tlb_search_cb() is added here to search TLB entry with specified address. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-28target/loongarch: Add tlb search callback in loongarch_tlb_search()Bibo Mao1-5/+15
With function loongarch_tlb_search(), it is to search TLB entry with speficied virtual address, the difference is selection with asid and global bit. Here add selection callback with asid and global bit. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-28target/loongarch: Fix page size set issue with CSR_STLBPSBibo Mao2-2/+4
When modify register CSR_STLBPS, the page size should come from input parameter rather than old value. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-09-28target/loongarch: Update TLB index selection methodBibo Mao1-7/+42
With function helper_tlbfill(), since there is no suitable TLB entry, new TLB will be added and flush one old TLB entry. The old TLB entry index is selected randomly now, instead it can be optimized as following: 1. invalid TLB entry can be selected at first. 2. TLB entry with other ASID can be selected secondly 3. random method is used by last. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>