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2025-05-22util/qemu-sockets: Introduce inet socket options controlling TCP keep-aliveJuraj Marcin4-0/+168
2025-05-22util/qemu-sockets: Refactor inet_parse() to use QemuOptsJuraj Marcin2-84/+270
2025-05-22util/qemu-sockets: Add support for keep-alive flag to passive socketsJuraj Marcin2-8/+5
2025-05-22util/qemu-sockets: Refactor success and failure paths in inet_listen_saddr()Juraj Marcin1-24/+27
2025-05-22util/qemu-sockets: Refactor setting client sockopts into a separate functionJuraj Marcin1-10/+19
2025-05-22io: Fix partial struct copy in qio_dns_resolver_lookup_sync_inet()Juraj Marcin1-16/+5
2025-05-22scripts/checkpatch: reject license boilerplate on new filesDaniel P. Berrangé1-0/+23
2025-05-22scripts/checkpatch: reimplement mandate for SPDX-License-IdentifierDaniel P. Berrangé1-0/+15
2025-05-22scripts/checkpatch: use new hook for MAINTAINERS update checkDaniel P. Berrangé1-18/+19
2025-05-22scripts/checkpatch: expand pattern for matching makefilesDaniel P. Berrangé1-1/+1
2025-05-22scripts/checkpatch: use new hook for file permissions checkDaniel P. Berrangé1-8/+11
2025-05-22scripts/checkpatch: use new hook for ACPI test data checkDaniel P. Berrangé1-32/+29
2025-05-22scripts/checkpatch: introduce tracking of file start/endDaniel P. Berrangé1-3/+107
2025-05-22scripts/checkpatch.pl: fix various indentation mistakesDaniel P. Berrangé1-49/+52
2025-05-22Revert "scripts: mandate that new files have SPDX-License-Identifier"Daniel P. Berrangé1-30/+0
2025-05-22crypto: fully drop built-in cipher providerDaniel P. Berrangé3-304/+31
2025-05-21tests: fix skipping cipher tests when AES is not availableDaniel P. Berrangé1-4/+9
2025-05-21tests: skip legacy qcow2 encryption test if AES is not availableDaniel P. Berrangé1-0/+7
2025-05-21tests: skip encrypted secret tests if AES is not availableDaniel P. Berrangé1-12/+16
2025-05-21ui/vnc: fix tight palette pixel encoding for 8/16-bpp formatsDaniel P. Berrangé1-4/+12
2025-05-21ui/vnc: take account of client byte order in pixman formatDaniel P. Berrangé4-11/+13
2025-05-21ui/vnc.c: replace big endian flag with byte order valueDaniel P. Berrangé5-7/+7
2025-05-20qom: reverse order of instance_post_init callsPaolo Bonzini2-5/+6
2025-05-20target/riscv: remove .instance_post_initPaolo Bonzini1-6/+2
2025-05-20target/riscv: convert Xiangshan Nanhu to RISCVCPUDefPaolo Bonzini1-57/+23
2025-05-20target/riscv: convert Ventana V1 to RISCVCPUDefPaolo Bonzini1-40/+35
2025-05-20target/riscv: convert TT Ascalon to RISCVCPUDefPaolo Bonzini1-67/+60
2025-05-20target/riscv: convert THead C906 to RISCVCPUDefPaolo Bonzini1-33/+28
2025-05-20target/riscv: generalize custom CSR functionalityPaolo Bonzini4-23/+40
2025-05-20target/riscv: th: make CSR insertion test a bit more intuitivePaolo Bonzini1-9/+4
2025-05-20target/riscv: convert SiFive U models to RISCVCPUDefPaolo Bonzini2-43/+37
2025-05-20target/riscv: convert ibex CPU models to RISCVCPUDefPaolo Bonzini1-23/+16
2025-05-20target/riscv: convert SiFive E CPU models to RISCVCPUDefPaolo Bonzini2-54/+21
2025-05-20target/riscv: convert dynamic CPU models to RISCVCPUDefPaolo Bonzini1-82/+31
2025-05-20target/riscv: convert bare CPU models to RISCVCPUDefPaolo Bonzini1-41/+17
2025-05-20target/riscv: convert profile CPU models to RISCVCPUDefPaolo Bonzini2-38/+48
2025-05-20target/riscv: convert abstract CPU classes to RISCVCPUDefPaolo Bonzini2-48/+46
2025-05-20target/riscv: add more RISCVCPUDef fieldsPaolo Bonzini3-1/+51
2025-05-20target/riscv: include default value in cpu_cfg_fields.h.incPaolo Bonzini2-12/+12
2025-05-20target/riscv: move RISCVCPUConfig fields to a header filePaolo Bonzini2-160/+173
2025-05-20target/riscv: merge riscv_cpu_class_init with the class_base functionPaolo Bonzini1-11/+10
2025-05-20target/riscv: store RISCVCPUDef struct directly in the classPaolo Bonzini8-29/+39
2025-05-20target/riscv: introduce RISCVCPUDefPaolo Bonzini2-9/+22
2025-05-20target/riscv: move satp_mode.{map,init} out of CPUConfigPaolo Bonzini3-30/+30
2025-05-20target/riscv: remove supported from RISCVSATPMapPaolo Bonzini2-11/+23
2025-05-20target/riscv: update max_satp_mode based on QOM propertiesPaolo Bonzini5-32/+24
2025-05-20target/riscv: cpu: store max SATP mode as a single integerPaolo Bonzini3-7/+8
2025-05-20target/riscv: assert argument to set_satp_mode_max_supported is validPaolo Bonzini1-1/+5
2025-05-20hw/riscv: acpi: only create RHCT MMU entry for supported typesPaolo Bonzini1-3/+6
2025-05-20qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabili...Zhao Liu1-2/+2