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2024-05-06xen: mapcache: Break out xen_invalidate_map_cache_single()Edgar E. Iglesias1-10/+15
Break out xen_invalidate_map_cache_single(). No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-10-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_invalidate_map_cache_entry_unlockedEdgar E. Iglesias1-10/+11
Add MapCache argument to xen_invalidate_map_cache_entry_unlocked. This is in preparation for supporting multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-9-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_replace_cache_entry_unlockedEdgar E. Iglesias1-4/+6
Add MapCache argument to xen_replace_cache_entry_unlocked in preparation for supporting multiple map caches. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-8-edgar.iglesias@gmail.com> [PMD: Remove last global mapcache pointer, reported by sstabellini] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Break out xen_ram_addr_from_mapcache_singleEdgar E. Iglesias1-6/+11
Break out xen_ram_addr_from_mapcache_single(), a multi-cache aware version of xen_ram_addr_from_mapcache. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-7-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_remap_bucket for multi-instanceEdgar E. Iglesias1-4/+5
Add MapCache argument to xen_remap_bucket in preparation to support multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-6-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_map_cache for multi-instanceEdgar E. Iglesias1-17/+18
Make xen_map_cache take a MapCache as argument. This is in prepaparation to support multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240430164939.925307-5-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor lock functions for multi-instanceEdgar E. Iglesias1-17/+17
Make the lock functions take MapCache * as argument. This is in preparation for supporting multiple caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240430164939.925307-4-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: let xen_ram_addr_from_mapcache() return -1 in case of not found entryJuergen Gross1-7/+3
Today xen_ram_addr_from_mapcache() will either abort() or return 0 in case it can't find a matching entry for a pointer value. Both cases are bad, so change that to return an invalid address instead. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <20231005181629.4046-5-vikram.garhwal@amd.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240430164939.925307-3-edgar.iglesias@gmail.com> [PMD: Keep xen_ram_addr_from_mapcache_not_found trace event] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06system: let qemu_map_ram_ptr() use qemu_ram_ptr_length()Juergen Gross1-33/+23
qemu_map_ram_ptr() and qemu_ram_ptr_length() share quite some code, so modify qemu_ram_ptr_length() a little bit and use it for qemu_map_ram_ptr(), too. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227223501.28475-4-vikram.garhwal@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-ID: <20240430164939.925307-2-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06user: Use get_task_state() helperPhilippe Mathieu-Daudé3-5/+6
Get the TaskState pointer calling get_task_state(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-11-philmd@linaro.org>
2024-05-06user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h'Philippe Mathieu-Daudé3-10/+20
While each user emulation implentation defines its own TaskState structure, both use the same get_task_state() declaration, in particular in common code (such gdbstub). Declare the method once in "accel/tcg/vcpu-state.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-10-philmd@linaro.org>
2024-05-06user: Forward declare TaskState type definitionPhilippe Mathieu-Daudé3-4/+5
Forward declare TaskState in "qemu/typedefs.h" so we can use it in generic headers like "hw/cpu/core.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-9-philmd@linaro.org>
2024-05-06accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetStatePhilippe Mathieu-Daudé5-12/+13
@plugin_mem_cbs is accessed by tcg generated code, move it to CPUNegativeOffsetState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429213050.55177-4-philmd@linaro.org>
2024-05-06accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCGPhilippe Mathieu-Daudé2-17/+17
So far cpu_plugin_mem_cbs_enabled() is only called from TCG, so reduce it to accel/tcg/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <5f59c754-44e5-4743-a2dd-87ef8e13eadf@linaro.org>
2024-05-06accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG pluginsPhilippe Mathieu-Daudé1-0/+4
qemu_plugin_vcpu_exit_hook() is specific to TCG plugins, so must be restricted to it in cpu_common_unrealizefn(), similarly to how qemu_plugin_create_vcpu_state() is restricted in the cpu_common_realizefn() counterpart. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429213050.55177-2-philmd@linaro.org>
2024-05-06accel/tcg: Update CPUNegativeOffsetState::can_do_io field documentationPhilippe Mathieu-Daudé1-4/+4
The @can_do_io field got moved from CPUState to CPUNegativeOffsetState in commit 464dacf609 ("accel/tcg: Move can_do_io to CPUNegativeOffsetState"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-14-philmd@linaro.org>
2024-05-06accel/tcg: Move user definition of cpu_interrupt() to user-exec.cPhilippe Mathieu-Daudé2-9/+8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-4-philmd@linaro.org>
2024-05-06accel/tcg: Access tcg_cflags with getter / setterPhilippe Mathieu-Daudé23-29/+44
Access the CPUState::tcg_cflags via tcg_cflags_has() and tcg_cflags_set() helpers. Mechanical change using the following Coccinelle spatch script: @@ expression cpu; expression flags; @@ - cpu->tcg_cflags & flags + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - (tcg_cflags_has(cpu, flags)) + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - cpu->tcg_cflags |= flags; + tcg_cflags_set(cpu, flags); Then manually moving the declarations, and adding both tcg_cflags_has() and tcg_cflags_set() definitions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-15-philmd@linaro.org>
2024-05-06accel/tcg: Use cpu_loop_exit_requested() in cpu_loop_exec_tb()Philippe Mathieu-Daudé1-5/+2
Do not open-code cpu_loop_exit_requested(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428214915.10339-9-philmd@linaro.org>
2024-05-06exec/cpu: Extract page-protection definitions to page-protection.hPhilippe Mathieu-Daudé59-30/+100
Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-protection.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-05-06exec/cpu: Remove duplicated PAGE_PASSTHROUGH definitionPhilippe Mathieu-Daudé1-6/+0
Missed in commit 58771921af ("include/exec: Move PAGE_* macros to common header"), PAGE_PASSTHROUGH ended being defined twice. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-8-philmd@linaro.org>
2024-05-06exec/cpu: Remove obsolete PAGE_RESERVED definitionPhilippe Mathieu-Daudé1-4/+0
We stopped using the PAGE_RESERVED definition in commit 50d25c8aec ("accel/tcg: Drop PAGE_RESERVED for CONFIG_BSD"). This completes commit 2e9a5713f0 ("Remove PAGE_RESERVED"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-7-philmd@linaro.org>
2024-05-06exec/cpu: Rename PAGE_BITS macro to PAGE_RWXBALATON Zoltan7-10/+10
This macro can be used to abbreviate PAGE_READ | PAGE_WRITE | PAGE_EXEC for which PAGE_RWX is a better name and renaming it also shows it is not related to TARGET_PAGE_BITS. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240505121008.44A0D4E602D@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06exec/cpu: Indent TARGET_PAGE_foo definitionsPhilippe Mathieu-Daudé1-12/+13
The TARGET_PAGE_foo definitions are defined with multiple level of #ifdef'ry. Indent it a bit for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-6-philmd@linaro.org>
2024-05-04target/alpha: Implement CF_PCRELRichard Henderson2-5/+47
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-10-philmd@linaro.org>
2024-05-04target/alpha: Split out gen_pc_dispRichard Henderson1-18/+23
Prepare for pcrel by not modifying cpu_pc before use, in the case of JSR. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-9-philmd@linaro.org>
2024-05-04target/alpha: Split out gen_goto_tbRichard Henderson1-37/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 5/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-8-philmd@linaro.org>
2024-05-04target/alpha: Simplify gen_bcond_internal()Philippe Mathieu-Daudé1-10/+9
Richard Henderson explained on IRC: bcond_internal() used to insist that both branch destination and branch fallthrough are use_goto_tb; if not, we'd use movcond to compute an indirect jump. But it's perfectly fine for e.g. the branch fallthrough to use_goto_tb, and the branch destination to use an indirect branch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 4/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-7-philmd@linaro.org>
2024-05-04target/alpha: Return DISAS_NORETURN onceRichard Henderson1-5/+4
Trivial change to make next commits easier to understand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 3/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-6-philmd@linaro.org>
2024-05-04target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURNRichard Henderson1-2/+4
Inline DISAS_PC_UPDATED switch case from alpha_tr_tb_stop(): switch (ctx->base.is_jmp) { ... case DISAS_PC_UPDATED: tcg_gen_lookup_and_goto_ptr(); break; Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 2/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-5-philmd@linaro.org>
2024-05-04target/alpha: Use DISAS_NEXT definition instead of magic '0' valueRichard Henderson1-2/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 1/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-4-philmd@linaro.org>
2024-05-04target/alpha: Hoist branch shift to initial decodeRichard Henderson1-3/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-3-philmd@linaro.org>
2024-05-04target/alpha: Use cpu_env in preference to ALPHA_CPURichard Henderson2-13/+10
ALPHA_CPU has a dynamic object type assert, which is unnecessary considering that these are all class hooks. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-2-philmd@linaro.org>
2024-05-03ui/cocoa.m: Drop old macOS-10.12-and-earlier compat ifdefsPeter Maydell1-13/+0
We only support the most recent two versions of macOS (currently macOS 13 Ventura and macOS 14 Sonoma), and our ui/cocoa.m code already assumes at least macOS 12 Monterey or better, because it uses NSScreen safeAreaInsets, which is 12.0-or-newer. Remove the ifdefs that were providing backwards compatibility for building on 10.12 and earlier versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240502142904.62644-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03target/sh4: Rename TCGv variables as manual for SUBV opcodePhilippe Mathieu-Daudé1-6/+10
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how underflow is calculated. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240430163125.77430-5-philmd@linaro.org>
2024-05-03target/sh4: Rename TCGv variables as manual for ADDV opcodePhilippe Mathieu-Daudé1-6/+10
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how overflow is calculated. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-4-philmd@linaro.org>
2024-05-03target/sh4: Fix SUBV opcodePhilippe Mathieu-Daudé3-1/+34
The documentation says: SUBV Rm, Rn Rn - Rm -> Rn, underflow -> T The overflow / underflow can be calculated as: T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 However we were using the incorrect: T = ((Rn ^ Rm) & (Result ^ Rm)) >> 31 Fix by using the Rn register instead of Rm. Add tests provided by Paul Cercueil. Cc: qemu-stable@nongnu.org Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <paul@crapouillou.net> Suggested-by: Paul Cercueil <paul@crapouillou.net> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2318 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-3-philmd@linaro.org>
2024-05-03target/sh4: Fix ADDV opcodePhilippe Mathieu-Daudé3-1/+31
The documentation says: ADDV Rm, Rn Rn + Rm -> Rn, overflow -> T But QEMU implementation was: ADDV Rm, Rn Rn + Rm -> Rm, overflow -> T Fix by filling the correct Rm register. Add tests provided by Paul Cercueil. Cc: qemu-stable@nongnu.org Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <paul@crapouillou.net> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-2-philmd@linaro.org>
2024-05-03MAINTAINERS: Update my email addressAnthony PERARD1-1/+1
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Paul Durrant <paul@xen.org> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240429154938.19340-1-anthony.perard@citrix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03plugins: Update stale commentPhilippe Mathieu-Daudé1-1/+1
"plugin_mask" was renamed as "event_mask" in commit c006147122 ("plugins: create CPUPluginState and migrate plugin_mask"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-05-03plugins/api: Only include 'exec/ram_addr.h' with system emulationPhilippe Mathieu-Daudé1-1/+1
"exec/ram_addr.h" shouldn't be used with user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-4-philmd@linaro.org>
2024-05-03coverity: Update user emulation regexpPhilippe Mathieu-Daudé1-1/+1
All user emulation headers are now under include/user/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-3-philmd@linaro.org>
2024-05-03user: Move 'thunk.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé5-6/+9
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-2-philmd@linaro.org>
2024-05-03user: Move 'abitypes.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé6-7/+7
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240503125202.35667-1-philmd@linaro.org>
2024-05-03exec: Include missing license in 'exec/cpu-common.h'Philippe Mathieu-Daudé1-2/+7
Commit 1ad2134f91 ("Hardware convenience library") extracted "cpu-common.h" from "cpu-all.h", which uses the LGPL-2.1+ license. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-5-philmd@linaro.org>
2024-05-03tests/bench: Add bufferiszero-benchRichard Henderson2-0/+48
Benchmark each acceleration function vs an aligned buffer of zeros. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Add simd acceleration for aarch64Richard Henderson1-0/+67
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely double-check with the compiler flags for __ARM_NEON and don't bother with a runtime check. Otherwise, model the loop after the x86 SSE2 function. Use UMAXV for the vector reduction. This is 3 cycles on cortex-a76 and 2 cycles on neoverse-n1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Simplify test_buffer_is_zero_next_accelRichard Henderson1-46/+35
Because the three alternatives are monotonic, we don't need to keep a couple of bitmasks, just identify the strongest alternative at startup. Generalize test_buffer_is_zero_next_accel and init_accel by always defining an accel_table array. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Introduce biz_accel_fn typedefRichard Henderson1-3/+4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Improve scalar variantRichard Henderson1-34/+51
Split less-than and greater-than 256 cases. Use unaligned accesses for head and tail. Avoid using out-of-bounds pointers in loop boundary conditions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>