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2025-10-03target/riscv: Fix endianness swap on compressed instructionsvhaudiquet1-3/+3
Three instructions were not using the endianness swap flag, which resulted in a bug on big-endian architectures. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3131 Buglink: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2123828 Fixes: e0a3054f18e ("target/riscv: add support for Zcb extension") Signed-off-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Cc: qemu-stable@nongnu.org Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250929115543.1648157-1-valentin.haudiquet@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03hw/riscv/riscv-iommu: Fixup PDT Nested WalkGuo Ren (Alibaba DAMO Academy)1-2/+141
Current implementation is wrong when iohgatp != bare. The RISC-V IOMMU specification has defined that the PDT is based on GPA, not SPA. So this patch fixes the problem, making PDT walk correctly when the G-stage table walk is enabled. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Cc: qemu-stable@nongnu.org Cc: Sebastien Boeuf <seb@rivosinc.com> Cc: Tomasz Jeznach <tjeznach@rivosinc.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Tested-by: Chen Pei <cp0613@linux.alibaba.com> Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Message-ID: <20250913041233.972870-1-guoren@kernel.org> [ Changes by AF: - Add braces to if statements ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 ↵Max Chou3-20/+66
and SEW=64 When XLEN is 32 and SEW is 64, the original implementation of vslide1up.vx and vslide1down.vx helper functions fills the 32-bit value of rs1 into the first element of the destination vector register (rd), which is a 64-bit element. This commit attempted to resolve the issue by extending the rs1 value to 64 bits during the TCG translation phase to ensure that the helper functions won't lost the higer 32 bits. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250124073325.2467664-1-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: rvv: Modify minimum VLEN according to enabled vector extensionsMax Chou1-2/+17
According to the RISC-V unprivileged specification, the VLEN should be greater or equal to the ELEN. This commit modifies the minimum VLEN based on the vector extensions and introduces a check rule for VLEN and ELEN. Extension Minimum VLEN * V 128 * Zve64[d|f|x] 64 * Zve32[f|x] 32 Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250923090729.1887406-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: rvv: Replace checking V by checking Zve32xMax Chou5-5/+7
The Zve32x extension will be applied by the V and Zve* extensions. Therefore we can replace the original V checking with Zve32x checking for both the V and Zve* extensions. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250923090729.1887406-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: Fix ssamoswap error handlingJim Shu3-0/+62
Follow the RISC-V CFI v1.0 spec [1] to fix the exception type when ssamoswap is disabled by xSSE. [1] RISC-V CFI spec v1.0, ch2.7 Atomic Swap from a Shadow Stack Location Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-4-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: Fix SSP CSR error handling in VU/VS modeJim Shu1-0/+2
In VU/VS mode, accessing $ssp CSR will trigger the virtual instruction exception instead of illegal instruction exception if SSE is disabled via xenvcfg CSRs. This is from RISC-V CFI v1.0 spec ch2.2.4. Shadow Stack Pointer Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-3-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: Fix the mepc when sspopchk triggers the exceptionJim Shu1-0/+1
When sspopchk is in the middle of TB and triggers the SW check exception, it should update PC from gen_update_pc(). If not, RISC-V mepc CSR will get wrong PC address which is still at the start of TB. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-2-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: do not use translator_ldl in opcode_atVladimir Isaev1-1/+2
opcode_at is used only in semihosting checks to match opcodes with expected pattern. This is not a translator and if we got following assert if page is not in TLB: qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion `offset == db->record_start + db->record_len' failed. Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything") Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250815140633.86920-1-vladimir.isaev@syntacore.com> [ Changes by AF: - Fixup header includes after rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03qemu/osdep: align memory allocations to 2M on RISC-VXuemei Liu1-1/+1
Similar to other architectures (e.g., x86_64, aarch64), utilizing THP on RISC-V KVM requires 2MiB-aligned memory blocks. Signed-off-by: Xuemei Liu <liu.xuemei1@zte.com.cn> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <20250924131803656Yqt9ZJKfevWkInaGppFdE@zte.com.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: use riscv_csrr in riscv_csr_readstove1-1/+1
Commit 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR") changed the behavior of riscv_csrrw, which would formerly be treated as read-only if the write mask were set to 0. Fixes an exception being raised when accessing read-only vector CSRs like vtype. Fixes: 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR") Signed-off-by: stove <stove@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250827203617.79947-1-stove@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN regPhilippe Mathieu-Daudé1-1/+1
Use the existing riscv_cpu_is_32bit() helper to check for 32-bit CPU. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20250924164515.51782-1-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03target/riscv: Save stimer and vstimer in CPU vmstateTANG Tiancheng1-0/+25
vmstate_riscv_cpu was missing env.stimer and env.vstimer. Without migrating these QEMUTimer fields, active S/VS-mode timer events are lost after snapshot or migration. Add VMSTATE_TIMER_PTR() entries to save and restore them. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911-timers-v3-4-60508f640050@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03hw/intc: Save timers array in RISC-V mtimer VMStateTANG Tiancheng2-2/+8
The current 'timecmp' field in vmstate_riscv_mtimer is insufficient to keep timers functional after migration. If an mtimer's entry in 'mtimer->timers' is active at the time the snapshot is taken, it means riscv_aclint_mtimer_write_timecmp() has written to 'mtimecmp' and scheduled a timer into QEMU's main loop 'timer_list'. During snapshot save, these active timers must also be migrated; otherwise, after snapshot load there is no mechanism to restore 'mtimer->timers' back into the 'timer_list', and any pending timer events would be lost. QEMU's migration framework commonly uses VMSTATE_TIMER_xxx macros to save and restore 'QEMUTimer' variables. However, 'timers' is a pointer array with variable length, and vmstate.h did not previously provide a helper macro for such type. This commit adds a new macro, 'VMSTATE_TIMER_PTR_VARRAY', to handle saving and restoring a variable-length array of 'QEMUTimer *'. We then use this macro to migrate the 'mtimer->timers' array, ensuring that timer events remain scheduled correctly after snapshot load. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911-timers-v3-3-60508f640050@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-03migration: Add support for a variable-length array of UINT32 pointersTANG Tiancheng1-0/+10
Add support for defining a vmstate field which is a variable-length array of pointers, and use this to define a VMSTATE_TIMER_PTR_VARRAY() which allows a variable-length array of QEMUTimer* to be used by devices. Message-id: 20250909-timers-v1-0-7ee18a9d8f4b@linux.alibaba.com Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911-timers-v3-2-60508f640050@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02hw/intc: Save time_delta in RISC-V mtimer VMStateTANG Tiancheng1-2/+3
In QEMU's RISC-V ACLINT timer model, 'mtime' is not stored directly as a state variable. It is computed on demand as: mtime = rtc_r + time_delta where: - 'rtc_r' is the current VM virtual time (in ticks) obtained via cpu_riscv_read_rtc_raw() from QEMU_CLOCK_VIRTUAL. - 'time_delta' is an offset applied when the guest writes a new 'mtime' value via riscv_aclint_mtimer_write(): time_delta = value - rtc_r Under this design, 'rtc_r' is assumed to be monotonically increasing during VM execution. Even if the guest writes an 'mtime' value smaller than the current one (making 'time_delta' negative in signed arithmetic, or underflow in unsigned arithmetic), the computed 'mtime' remains correct because 'rtc_r_new > rtc_r_old': mtime_new = rtc_r_new + (value - rtc_r_old) However, this monotonicity assumption breaks on snapshot load. Before restoring a snapshot, QEMU resets the guest, which calls riscv_aclint_mtimer_reset_enter() to set 'mtime' to 0 and recompute 'time_delta' as: time_delta = 0 - rtc_r_reset Here, the time_delta differs from the value that was present when the snapshot was saved. As a result, subsequent reads produce a fixed offset from the true mtime. This can be observed with the 'date' command inside the guest: after loading a snapshot, the reported time appears "frozen" at the save point, and only resumes correctly after the guest has run long enough to compensate for the erroneous offset. The fix is to treat 'time_delta' as part of the device's migratable state and save/restore it via vmstate. This preserves the correct relation between 'rtc_r' and 'mtime' across snapshot save/load, ensuring 'mtime' continues incrementing from the precise saved value after restore. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911-timers-v3-1-60508f640050@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02hw/char: sifive_uart: Add newline to error messageFrank Chang1-1/+1
Adds a missing newline character to the error message. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911160647.5710-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02hw/char: sifive_uart: Remove outdated comment about Tx FIFOFrank Chang1-6/+0
Since Tx FIFO is now implemented using "qemu/fifo8.h", remove the comment that no longer reflects the current implementation. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911160647.5710-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02hw/char: sifive_uart: Avoid pushing Tx FIFO when size is zeroFrank Chang1-1/+3
There's no need to call fifo8_push_all() when size is zero. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911160647.5710-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02hw/char: sifive_uart: Raise IRQ according to the Tx/Rx watermark thresholdsFrank Chang1-12/+12
Currently, the SiFive UART raises an IRQ whenever: 1. ie.txwm is enabled. 2. ie.rxwm is enabled and the Rx FIFO is not empty. It does not check the watermark thresholds set by software. However, since commit [1] changed the SiFive UART character printing from synchronous to asynchronous, Tx overflows may occur, causing characters to be dropped when running Linux because: 1. The Linux SiFive UART driver sets the transmit watermark level to 1 [2], meaning a transmit watermark interrupt is raised whenever a character is enqueued into the Tx FIFO. 2. Upon receiving a transmit watermark interrupt, the Linux driver transfers up to a full Tx FIFO's worth of characters from the Linux serial transmit buffer [3], without checking the txdata.full flag before transferring multiple characters [4]. To fix this issue, we must honor the Tx/Rx watermark thresholds and raise interrupts only when the Tx threshold is exceeded or the Rx threshold is undercut. [1] 53c1557b230986ab6320a58e1b2c26216ecd86d5 [2] https://github.com/torvalds/linux/blob/master/drivers/tty/serial/sifive.c#L1039 [3] https://github.com/torvalds/linux/blob/master/drivers/tty/serial/sifive.c#L538 [4] https://github.com/torvalds/linux/blob/master/drivers/tty/serial/sifive.c#L291 Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250911160647.5710-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02roms/opensbi: Update to v1.7Daniel Henrique Barboza3-0/+0
Update OpenSBI and the pre-built opensbi32 and opensbi64 images to version 1.7. It has been almost an year since we last updated OpenSBI (at the time, up to v1.5.1) and we're missing a lot of good stuff from both v1.6 and v1.7, including SBI 3.0 and RPMI 1.0. The changelog is too large and tedious to post in the commit msg so I encourage refering to [1] and [2] to see the new features we're adding into the QEMU roms. [1] https://github.com/riscv-software-src/opensbi/releases/tag/v1.6 [2] https://github.com/riscv-software-src/opensbi/releases/tag/v1.7 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02target/riscv: implement MonitorDef HMP APIDaniel Henrique Barboza2-0/+149
The MonitorDef API is related to two HMP monitor commands: 'p' and 'x': (qemu) help p print|p /fmt expr -- print expression value (use $reg for CPU register access) (qemu) help x x /fmt addr -- virtual memory dump starting at 'addr' For x86, one of the few targets that implements it, it is possible to print the PC register value with $pc and use the PC value in the 'x' command as well. Those 2 commands are hooked into get_monitor_def(), called by exp_unary() in hmp.c. The function tries to fetch a reg value in two ways: by reading them directly via a target_monitor_defs array or using a target_get_monitor_def() helper. In RISC-V we have *A LOT* of registers and this number will keep getting bigger, so we're opting out of an array declaration. We're able to retrieve all regs but vregs because the API only fits an uint64_t and vregs have 'vlen' size that are bigger than that. With this patch we can do things such as: - print CSRs and use their val in expressions: (qemu) p $mstatus 0xa000000a0 (qemu) p $mstatus & 0xFF 0xa0 - dump the next 10 insn from virtual memory starting at x1 (ra): (qemu) x/10i $ra 0xffffffff80958aea: a9bff0ef jal ra,-1382 # 0xffffffff80958584 0xffffffff80958aee: 10016073 csrrsi zero,sstatus,2 0xffffffff80958af2: 60a2 ld ra,8(sp) 0xffffffff80958af4: 6402 ld s0,0(sp) 0xffffffff80958af6: 0141 addi sp,sp,16 0xffffffff80958af8: 8082 ret 0xffffffff80958afa: 10016073 csrrsi zero,sstatus,2 0xffffffff80958afe: 8082 ret 0xffffffff80958b00: 1141 addi sp,sp,-16 0xffffffff80958b02: e422 sd s0,8(sp) (qemu) Suggested-by: Dr. David Alan Gilbert <dave@treblig.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250703130815.1592493-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02linux-user/syscall.c: sync RISC-V hwprobe with LinuxDaniel Henrique Barboza1-0/+89
It has been awhile since the last sync. Let's bring QEMU hwprobe support on par with Linux 6.17-rc4. A lot of new RISCV_HWPROBE_KEY_* entities are added but this patch is only adding support for ZICBOM_BLOCK_SIZE. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250903164043.2828336-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02docs/interop/firmware: Add riscv64 to FirmwareArchitectureAndrea Bolognani1-1/+3
Descriptors using this value have been shipped for years by distros, so we just need to update the spec to match reality. Signed-off-by: Andrea Bolognani <abologna@redhat.com> Reviewed-by: Kashyap Chamarthy <kchamart@redhat.com> Message-ID: <20250910121501.676219-1-abologna@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-02hw/riscv/riscv-iommu: Fix MSI table size limitAndrew Jones1-4/+7
The MSI table is not limited to 4k. The only constraint the table has is that its base address must be aligned to its size, ensuring no offsets of the table size will overrun when added to the base address (see "8.5. MSI page tables" of the AIA spec). Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250904132723.614507-2-ajones@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-10-01migration-test: strv parameterSteve Sistare2-0/+18
Define migrate_set_parameter_strv. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-19-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01migration-test: migrate_argsSteve Sistare2-24/+43
Define the subroutine migrate_args to return the arguments that are used to exec the source or target qemu process. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-18-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01migration-test: misc exportsSteve Sistare4-0/+12
Export misc definitions needed by the cpr-exec test. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-17-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01migration-test: shm path accessorSteve Sistare1-1/+6
Define an accessor for the shm path. It will be referenced from multiple sites in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-16-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01migration-test: only_source optionSteve Sistare2-9/+17
Add the only_source option, analogous to only_target. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-15-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: qtest_init_after_execSteve Sistare2-0/+27
Define a function to create a QTestState object representing the state of QEMU after old QEMU exec's new QEMU. This is needed for testing the cpr-exec migration mode. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-14-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: qtest_qemu_spawn_funcSteve Sistare1-5/+13
Allow the qtest_qemu_spawn caller to pass the function to be called to perform the spawn. The opaque argument is needed by a new spawn function in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-13-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: qtest_create_test_stateSteve Sistare1-7/+14
Refactor qtest_spawn_qemu and create a subroutine to create a QTestState object, to be used in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-12-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: qtest_qemu_argsSteve Sistare2-23/+39
Define an accessor that returns all the arguments used to exec QEMU. Collect the arguments that were passed to qtest_spawn_qemu, plus the trace arguments that were composed inside qtest_spawn_qemu, and move them to a new function qtest_qemu_args. This will be needed to test the cpr-exec migration mode. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-11-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: export qtest_qemu_binarySteve Sistare2-1/+10
Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/1759332851-370353-10-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: optimize qtest_get_machinesSteve Sistare1-5/+7
qtest_get_machines returns the machines supported by the QEMU binary described by an environment variable and caches the result. If the next call to qtest_get_machines passes the same variable name, the cached result is returned, but if the name changes, the caching is defeated. To make caching more effective, remember the path of the QEMU binary instead. Different env vars, eg QTEST_QEMU_BINARY_SRC and QTEST_QEMU_BINARY_DST, usually resolve to the same path. Before the optimization, the test /x86_64/migration/precopy/unix/plain exec's QEMU and calls query-machines 3 times. After optimization, that only happens once. This does not significantly speed up the tests, but it reduces QTEST_LOG output, and launches fewer QEMU instances, making it easier to debug problems. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <87h5ymdzrf.fsf@pond.sub.org> Link: https://lore.kernel.org/qemu-devel/1758290310-349623-1-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest/migration: Fix cpr-tests in case the machine is not availableThomas Huth3-4/+9
When QEMU has been compiled with "--without-default-devices", the migration cpr-tests are currently failing since the first test leaves a socket file behind that avoids that the second test can be initialized correctly. Make sure that we delete the socket file in case that the migrate_start() failed due to the missing machine. Signed-off-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250930090932.235151-1-thuth@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tests/qtest: Add missing checks for the availability of machinesThomas Huth3-3/+5
When QEMU has been compiled with "--without-default-devices", the machines might not be available in the binary. Let's properly check for the machines before running the tests to avoid that they are failing in this case. Signed-off-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250930090444.234431-1-thuth@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-10-01tracetool/syslog: add Rust supportTanish Desai6-2/+57
The syslog backend needs the syslog function from libc and the LOG_INFO enum value; they are re-exported as "::trace::syslog" and "::trace::LOG_INFO" so that device crates do not all have to add the libc dependency, but otherwise there is nothing special. Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-17-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01tracetool/ftrace: add Rust supportTanish Desai3-2/+48
Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-16-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01tracetool/log: add Rust supportTanish Desai3-2/+54
Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-15-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01log: change qemu_loglevel to unsignedPaolo Bonzini4-26/+26
Bindgen makes the LOG_* constants unsigned, even if they are defined as (1 << 15): pub const LOG_TRACE: u32 = 32768; Make them unsigned in C as well through the BIT() macro, and also change the type of the variable that they are used with. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-14-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01tracetool/simple: add Rust supportTanish Desai3-0/+49
Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-13-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01rust: pl011: add tracepointsPaolo Bonzini5-24/+50
Finally bring parity between C and Rust versions of the PL011 device model. Changing some types of the arguments makes for nicer Rust code; C does not care. :) Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-12-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01rust: qdev: add minimal clock bindingsPaolo Bonzini1-0/+33
Add the minimal support that is needed by pl011's event and tracepoint. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-11-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01rust: add trace crateTanish Desai7-2/+83
The trace crate is a minimal container for dependencies of tracepoints (so that they do not have to be imported in all the crates that use tracepoints); it also contains a macro called "include_trace!" that is able to find the right include file from the trace/ directory. [Write commit message, add #[allow()]. - Paolo] Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-10-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01tracetool: Add Rust format supportTanish Desai2-0/+219
Generating .rs files makes it possible to support tracing in rust. This support comprises a new format, and common code that converts the C expressions in trace-events to Rust. In particular, types need to be converted, and PRI macros expanded. As of this commit no backend generates Rust code, but it is already possible to use tracetool to generate Rust sources; they are not functional but they compile and contain tracepoint functions. [Move Rust argument conversion from Event to Arguments; string support. - Paolo] Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20250929154938.594389-9-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01tracetool/backend: remove redundant trace event checksTanish Desai5-28/+20
Use CHECK_TRACE_EVENT_GET_STATE in log, syslog, dtrace and simple backend, so that the "if (trace_event_get_state)" is created from common code and unified when multiple backends are active. When a single backend is active there is no code change (except for the log backend, as shown in tests/tracetool/log.h), but the code in the backends is simpler. Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250929154938.594389-8-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01tracetool: add CHECK_TRACE_EVENT_GET_STATETanish Desai2-16/+36
Add a new attribute CHECK_TRACE_EVENT_GET_STATE to the backends. When present and True, the code generated by the generate function is wrapped in a conditional that checks whether the event is enabled; this removes the need for repeating the same conditional in multiple backends. Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250929154938.594389-7-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-10-01trace/ftrace: move snprintf+write from tracepoints to ftrace.cPaolo Bonzini4-32/+24
This simplifies the Python code and reduces the size of the tracepoints. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250929154938.594389-6-pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>