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2025-03-07target/loongarch: fix 'make check-functional' failedSong Gao1-0/+12
some tlb instructions get the tlb_ps from tlb->misc but the value may has been initialized to 0,just check the tlb_ps skip the function and write a log. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20250305063311.830674-2-gaosong@loongson.cn>
2025-03-06include: Poison TARGET_PHYS_ADDR_SPACE_BITS definitionPhilippe Mathieu-Daudé1-0/+1
Ensure common code never use this target specific definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305153929.43687-4-philmd@linaro.org>
2025-03-06system: Open-code qemu_init_arch_modules() using target_name()Philippe Mathieu-Daudé3-12/+6
Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules") but using target_name() instead of the target specific 'TARGET_NAME' definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305005225.95051-3-philmd@linaro.org>
2025-03-06target/i386: Mark WHPX APIC region as little-endianPhilippe Mathieu-Daudé1-1/+1
This device is only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250212113938.38692-6-philmd@linaro.org>
2025-03-06target/alpha: Do not mix exception flags and FPCR bitsPhilippe Mathieu-Daudé1-8/+7
get_float_exception_flags() returns exception flags, which are distinct from the FPCR bits used as error code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250211162604.83446-1-philmd@linaro.org>
2025-03-06target/riscv: Convert misa_mxl_max using GLib macrosPhilippe Mathieu-Daudé1-5/+5
Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-6-philmd@linaro.org>
2025-03-06target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXLPhilippe Mathieu-Daudé2-2/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-5-philmd@linaro.org>
2025-03-06target/xtensa: Finalize config in xtensa_register_core()Philippe Mathieu-Daudé2-3/+4
Make XtensaConfigList::config not const. Only modify XtensaConfig within xtensa_register_core(), when the class is registered, not when it is initialized. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20250210133134.90879-4-philmd@linaro.org>
2025-03-06target/sparc: Constify SPARCCPUClass::cpu_defPhilippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-3-philmd@linaro.org>
2025-03-06target/i386: Constify X86CPUModel usesPhilippe Mathieu-Daudé2-5/+5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-2-philmd@linaro.org>
2025-03-06disas: Remove target_words_bigendian() call in initialize_debug_target()Philippe Mathieu-Daudé1-6/+2
All CPUClass implementating disas_set_info() must set the disassemble_info::endian value. Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before calling the CPUClass::disas_set_info() handler, then asserting %endian is not BFD_ENDIAN_UNKNOWN after the call. This allows removing the target_words_bigendian() call in disas/. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250210212931.62401-11-philmd@linaro.org>
2025-03-06target/xtensa: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-10-philmd@linaro.org>
2025-03-06target/sh4: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-9-philmd@linaro.org>
2025-03-06target/riscv: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+9
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-8-philmd@linaro.org>
2025-03-06target/ppc: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback always set\ the disassemble_info::endian field. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-7-philmd@linaro.org>
2025-03-06target/mips: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-5/+5
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-6-philmd@linaro.org>
2025-03-06target/microblaze: Set disassemble_info::endian value in disas_set_infoPhilippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-5-philmd@linaro.org>
2025-03-06target/arm: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-7/+3
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-4-philmd@linaro.org>
2025-03-06target: Set disassemble_info::endian value for big-endian targetsPhilippe Mathieu-Daudé5-0/+5
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for big-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-3-philmd@linaro.org>
2025-03-06target: Set disassemble_info::endian value for little-endian targetsPhilippe Mathieu-Daudé6-0/+6
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for little-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-2-philmd@linaro.org>
2025-03-06target/mips: Fix possible MSA int overflowDenis Rastyogin1-3/+3
Fix possible overflow in 1 << (DF_BITS(df) - 2) when DF_BITS(df) is 64 by using a 64-bit integer for the shift operation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Reported-by: Dmitriy Fedin <d.fedin@fobos-nt.ru> Signed-off-by: Denis Rastyogin <gerben@altlinux.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20250124122707.54264-1-gerben@altlinux.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-06target/tricore: Ensure not being build on user emulationPhilippe Mathieu-Daudé1-0/+4
Currently only system emulation is supported. Assert no target code is built for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-4-philmd@linaro.org>
2025-03-06target/rx: Ensure not being build on user emulationPhilippe Mathieu-Daudé3-12/+4
Currently only system emulation is supported. Assert no target code is built for user emulation. Remove #ifdef'ry since more work is required before being able to emulate a user process. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-3-philmd@linaro.org>
2025-03-06target/hexagon: Ensure not being build on system emulationPhilippe Mathieu-Daudé1-0/+4
Currently only user emulation is supported. Assert no target code is built for system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Message-Id: <20250121142341.17001-2-philmd@linaro.org>
2025-03-06target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize()Philippe Mathieu-Daudé3-4/+4
OpenRISC timer is architecturally tied to the CPU. It doesn't belong to the machine init() code to instanciate it: move its creation when a vCPU is realized (after being created). Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250114231304.77150-1-philmd@linaro.org>
2025-03-06target/i386/hvf: Variable type fixup in decoderPhil Dennis-Jordan1-2/+2
decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Fixes: ff2de1668c9 ("i386: hvf: remove addr_t") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241209203629.74436-9-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-06target/microblaze: Consider endianness while translating codePhilippe Mathieu-Daudé2-2/+10
Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-17-philmd@linaro.org>
2025-03-06target/microblaze: Introduce mo_endian() helperPhilippe Mathieu-Daudé1-4/+10
mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-16-philmd@linaro.org>
2025-03-06target/microblaze: Set MO_TE once in do_load() / do_store()Philippe Mathieu-Daudé1-16/+20
All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-15-philmd@linaro.org>
2025-03-06target/microblaze: Explode MO_TExx -> MO_TE | MO_xxPhilippe Mathieu-Daudé1-18/+18
Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20241105130431.22564-14-philmd@linaro.org>
2025-03-06hw/core/generic-loader: Do not open-code cpu_set_pc()Philippe Mathieu-Daudé1-4/+1
Directly call cpu_set_pc() instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250122093028.52416-2-philmd@linaro.org>
2025-03-06cpus: Restrict cpu_get_memory_mapping() to system emulationPhilippe Mathieu-Daudé1-2/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-5-philmd@linaro.org>
2025-03-06cpus: Have cpu_exec_initfn() per user / system emulationPhilippe Mathieu-Daudé3-9/+12
Slighly simplify cpu-target.c again by extracting cpu_exec_initfn() to cpu-{system,user}.c, adding an empty stub for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-19-philmd@linaro.org>
2025-03-06cpus: Have cpu_class_init_props() per user / system emulationPhilippe Mathieu-Daudé5-59/+72
Rather than maintaining a mix of system / user code for CPU class properties, move system properties to cpu-system.c and user ones to the new cpu-user.c unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-18-philmd@linaro.org>
2025-03-06cpus: Restrict cpu_common_post_load() code to TCGPhilippe Mathieu-Daudé1-16/+19
CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7 ("Use a dedicated function to request exit from execution loop"), tlb_flush() and tb_flush() are related to TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-17-philmd@linaro.org>
2025-03-06cpus: Fix style in cpu-target.cPhilippe Mathieu-Daudé1-3/+6
Fix style on code we are going to modify. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-16-philmd@linaro.org>
2025-03-06accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.hPhilippe Mathieu-Daudé1-2/+0
Missed in commit b86f59c7155 ("accel: replace struct CpusAccel with AccelOpsClass") which removed the single CpusAccel use. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-7-philmd@linaro.org>
2025-03-06accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.cPhilippe Mathieu-Daudé2-88/+82
cpu_memory_rw_debug() system implementation is defined in system/physmem.c. Move the user one to accel/tcg/user-exec.c to simplify cpu-target.c maintenance. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-6-philmd@linaro.org>
2025-03-06accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug()Philippe Mathieu-Daudé1-15/+2
We checked the page flags with page_get_flags(), so locking the page is superfluous. Remove the lock_user() calls and directly use g2h() in place. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-5-philmd@linaro.org>
2025-03-06accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() functionPhilippe Mathieu-Daudé1-2/+4
Simplify user implementation of cpu_memory_rw_debug() by taking the mmap lock globally. See commit 87ab2704296 ("linux-user: Allow gdbstub to ignore page protection") for why this lock is necessary. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-4-philmd@linaro.org>
2025-03-06accel/tcg: Include missing bswap headers in user-exec.cPhilippe Mathieu-Daudé1-0/+2
Commit 35c653c4029 ("tcg: Add 128-bit guest memory primitives") introduced the use of bswap128() which is declared in "qemu/int128.h", commit de95016dfbf ("accel/tcg: Implement helper_{ld,st}*_mmu for user-only") introduced the other bswap*() uses, which are declared in "qemu/bswap.h". Include the missing headers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-3-philmd@linaro.org>
2025-03-06accel/accel-cpu-target.h: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+3
CPU_RESOLVING_TYPE is declared per target in "cpu.h". Include it (along with "qom/object.h") to avoid when moving code around: include/accel/accel-cpu-target.h:26:50: error: expected ')' 26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) | ^ include/accel/accel-cpu-target.h:23:33: note: expanded from macro 'TYPE_ACCEL_CPU' 23 | #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE | ^ include/accel/accel-cpu-target.h:26:1: note: to match this '(' 26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) | ^ include/qom/object.h:196:14: note: expanded from macro 'DECLARE_CLASS_CHECKERS' 196 | { return OBJECT_GET_CLASS(ClassType, obj, TYPENAME); } \ | ^ include/qom/object.h:558:5: note: expanded from macro 'OBJECT_GET_CLASS' 558 | OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name) | ^ include/qom/object.h:544:74: note: expanded from macro 'OBJECT_CLASS_CHECK' 544 | ((class_type *)object_class_dynamic_cast_assert(OBJECT_CLASS(class), (name), \ | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-13-philmd@linaro.org>
2025-03-06accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h'Philippe Mathieu-Daudé19-8/+12
The heavily imported "system/cpus.h" header includes "accel-ops.h" to get AccelOpsClass type declaration. Reduce headers pressure by forward declaring it in "qemu/typedefs.h", where we already declare the AccelCPUState type. Reduce "system/cpus.h" inclusions by only including "system/accel-ops.h" when necessary. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-14-philmd@linaro.org>
2025-03-06accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'Philippe Mathieu-Daudé10-11/+11
AccelCPUClass is for accelerator to initialize target specific features of a vCPU. Not really related to hardware emulation, rename "hw/core/accel-cpu.h" as "accel/accel-cpu-target.h" (using the explicit -target suffix). More importantly, target specific header often access the target specific definitions which are in each target/FOO/cpu.h header, usually included generically as "cpu.h" relative to target/FOO/. However, there is already a "cpu.h" in hw/core/ which takes precedence. This change allows "accel-cpu-target.h" to include a target "cpu.h". Mechanical change doing: $ git mv include/hw/core/accel-cpu.h \ include/accel/accel-cpu-target.h $ sed -i -e 's,hw/core/accel-cpu.h,accel/accel-cpu-target.h,' \ $(git grep -l hw/core/accel-cpu.h) and renaming header guard 'ACCEL_CPU_TARGET_H'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-12-philmd@linaro.org>
2025-03-06accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'Philippe Mathieu-Daudé37-36/+36
TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-11-philmd@linaro.org>
2025-03-06accel/tcg: Restrict 'icount_align_option' global to TCGPhilippe Mathieu-Daudé4-3/+4
Since commit 740b1759734 ("cpu-timers, icount: new modules") we don't need to expose icount_align_option to all the system code, we can restrict it to TCG. Since it is used as a boolean, declare it as 'bool' type. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-10-philmd@linaro.org>
2025-03-06accel/tcg: Restrict tlb_init() / destroy() to TCGPhilippe Mathieu-Daudé3-16/+22
Move CPU TLB related methods to accel/tcg/ scope, in "internal-common.h". Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-9-philmd@linaro.org>
2025-03-06accel/tcg: Build tcg_flags helpers as common codePhilippe Mathieu-Daudé2-32/+33
While cpu-exec.c is build for each target,tcg_flags helpers aren't target specific. Move them to cpu-exec-common.c to build them once. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-8-philmd@linaro.org>
2025-03-06accel/tcg: Remove pointless initialization of cflags_next_tbPhilippe Mathieu-Daudé1-1/+0
cflags_next_tb is always re-initialized in the CPU Reset() handler in cpu_common_reset_hold(), no need to initialize it in cpu_common_initfn(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-13-philmd@linaro.org>
2025-03-06accel/accel: Make TYPE_ACCEL abstractPhilippe Mathieu-Daudé1-0/+1
There is no generic acceleration, we have to use specific implementations. Make the base class abstract. Fixes: b14a0b7469fa ("accel: Use QOM classes for accel types") Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200129212345.20547-3-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>