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2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang4-50/+50
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang4-45/+121
2021-12-20target/riscv: rvv-1.0: slide instructionsFrank Chang1-7/+12
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2-5/+2
2021-12-20target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang1-9/+0
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang2-11/+2
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang4-51/+51
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang3-26/+17
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang4-6/+102
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang4-0/+133
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang2-0/+29
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang3-26/+21
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang1-2/+14
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang2-9/+37
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang4-12/+43
2021-12-20target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang1-10/+22
2021-12-20target/riscv: rvv-1.0: element index instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang2-3/+9
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang3-8/+7
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang4-7/+7
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang4-8/+9
2021-12-20target/riscv: rvv-1.0: floating-point classify instructionsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: floating-point square-root instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang3-13/+42
2021-12-20target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang2-51/+80
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang4-0/+176
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang4-109/+38
2021-12-20target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...Frank Chang1-4/+4
2021-12-20target/riscv: rvv-1.0: index load and store instructionsFrank Chang4-151/+145
2021-12-20target/riscv: rvv-1.0: stride load and store instructionsFrank Chang4-447/+300
2021-12-20target/riscv: rvv-1.0: configure instructionsFrank Chang2-36/+40
2021-12-20target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang4-316/+0
2021-12-20target/riscv: rvv:1.0: add translation-time nan-box helper functionFrank Chang1-1/+34
2021-12-20target/riscv: introduce more imm value modes in translator functionsFrank Chang1-49/+66
2021-12-20target/riscv: rvv-1.0: update check functionsFrank Chang1-208/+507
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang2-1038/+891
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang3-16/+42
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang4-187/+111
2021-12-20target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang1-0/+5
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu2-0/+8
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei2-0/+24
2021-12-20target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang1-13/+0
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang4-14/+109
2021-12-20target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei2-1/+2
2021-12-20target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang1-0/+1
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei4-2/+33