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2021-09-25qapi: Tidy up unusual line breaksMarkus Armbruster4-24/+24
Break lines between members instead of within members. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210917143134.412106-2-armbru@redhat.com>
2021-09-24hw/nvme: Return error for fused operationsPankaj Raghav1-0/+8
Currently, FUSED operations are not supported by QEMU. As per the 1.4 SPEC, controller should abort the command that requested a fused operation with an INVALID FIELD error code if they are not supported. Changes from v1: Added FUSE flag check also to the admin cmd processing as the FUSED operations are mentioned in the general SQE section in the SPEC. Signed-off-by: Pankaj Raghav <p.raghav@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2021-09-24hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar2-3/+17
Fix is added to check for reserved value in select field for namespace attachment CC: Minwoo Im <minwoo.im.dev@gmail.com> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2021-09-24hw/nvme: fix validation of ASQ and ACQKlaus Jensen2-10/+0
Address 0x0 is a valid address. Fix the admin submission and completion queue address validation to not error out on this. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
2021-09-23linux-user/aarch64: Use force_sig_fault()Peter Maydell1-25/+8
Use the new force_sig_fault() function instead of setting up a target_siginfo_t and calling queue_signal(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-8-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-23linux-user/arm: Use force_sig_fault()Peter Maydell1-38/+15
Use the new force_sig_fault() function instead of setting up a target_siginfo_t and calling queue_signal(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-7-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-23linux-user: Provide new force_sig_fault() functionPeter Maydell2-0/+18
In many places in the linux-user code we need to queue a signal for the guest using the QEMU_SI_FAULT si_type. This requires that the caller sets up and passes us a target_siginfo, including setting the appropriate part of the _sifields union for the si_type. In a number of places the code forgets to set the _sifields union field. Provide a new force_sig_fault() function, which does the same thing as the Linux kernel function of that name -- it takes the signal number, the si_code value and the address to use in _sifields._sigfault, and assembles the target_siginfo itself. This makes the callsites simpler and means it's harder to forget to pass in an address value. We follow force_sig() and the kernel's force_sig_fault() in not requiring the caller to pass in the CPU pointer but always acting on the CPU of the current thread. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-6-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-23linux-user: Zero out target_siginfo_t in force_sig()Peter Maydell1-1/+1
The target_siginfo_t we populate in force_sig() will eventually get copied onto the target's stack. Zero it out so that any extra padding in the sifields union is consistently zero when the guest sees it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-5-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-23linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPEPeter Maydell1-7/+4
In the Arm target code, when the fpa11 emulation code tells us we need to send the guest a SIGFPE, we do this with queue_signal(), but we are using the wrong si_type, and we aren't setting the _sifields union members corresponding to either the si_type we are using or the si_type we should be using. As the existing comment notes, the kernel code for this calls the old send_sig() function to deliver the signal. This eventually results in the kernel's signal handling code fabricating a siginfo_t with a SI_KERNEL code and a zero pid and uid. For QEMU this means we need to use QEMU_SI_KILL. We already have a function for that: force_sig() sets up the whole target_siginfo_t the way we need it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-23linux-user/arm: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell1-0/+1
When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field to the PC where the breakpoint/singlestep trap occurred; this is what the kernel does for this signal for this architecture. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-3-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-23linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell1-0/+1
When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field to the PC where the breakpoint/singlestep trap occurred; this is what the kernel does for this signal for this architecture. Fixes: Coverity 1459154 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-2-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-21tcg/riscv: Remove add with zero on user-only memory accessRichard Henderson1-8/+2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson12-21/+23
While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/sparc: Introduce tcg_out_mov_delayRichard Henderson1-6/+15
This version of tcg_out_mov is emits a nop to fill the delay slot if the move is not required. The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/sparc: Drop inline markersRichard Henderson1-23/+22
Let the compiler decide about inlining. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Drop special alignment for code_gen_bufferRichard Henderson1-91/+0
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Unset TCG_TARGET_HAS_direct_jumpRichard Henderson2-25/+10
Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subrRichard Henderson1-2/+4
Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Drop inline markersRichard Henderson1-49/+27
Let the compiler decide about inlining. Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21accel/tcg: Restrict cpu_handle_halt() to sysemuPhilippe Mathieu-Daudé1-2/+4
Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn(): case EXCP_HALTED: /* during start-up the vCPU is reset and the thread is * kicked several times. If we don't ensure we go back * to sleep in the halted state we won't cleanly * start-up when the vCPU is enabled. * * cpu->halted should ensure we sleep in wait_io_event */ g_assert(cpu->halted); break; qemu_wait_io_event() is sysemu-specific, so we can restrict the cpu_handle_halt() call in cpu_exec() to system emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210912172731.789788-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson22-89/+13
There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21target/arm: Optimize MVE 1op-immediate insnsPeter Maydell1-5/+21
Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to use TCG vector ops when possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-13-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE VSLI and VSRIPeter Maydell1-2/+2
Optimize the MVE shift-and-insert insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-12-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE VSHLL and VMOVLPeter Maydell1-8/+59
Optimize the MVE VSHLL insns by using TCG vector ops when possible. This includes the VMOVL insn, which we handle in mve.decode as "VSHLL with zero shift count". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-11-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE VSHL, VSHR immediate formsPeter Maydell1-20/+63
Optimize the MVE VSHL and VSHR immediate forms by using TCG vector ops when possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-10-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE VMVNPeter Maydell1-1/+1
Optimize the MVE VMVN insn by using TCG vector ops when possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-9-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE VDUPPeter Maydell1-4/+8
Optimize the MVE VDUP insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-8-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE VNEG, VABSPeter Maydell1-10/+22
Optimize the MVE VNEG and VABS insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-7-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE arithmetic opsPeter Maydell1-9/+11
Optimize MVE arithmetic ops when we have a TCG vector operation we can use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-6-peter.maydell@linaro.org
2021-09-21target/arm: Optimize MVE logic opsPeter Maydell1-15/+36
When not predicating, implement the MVE bitwise logical insns directly using TCG vector operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-5-peter.maydell@linaro.org
2021-09-21target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell7-9/+92
Our current codegen for MVE always calls out to helper functions, because some byte lanes might be predicated. The common case is that in fact there is no predication active and all lanes should be updated together, so we can produce better code by detecting that and using the TCG generic vector infrastructure. Add a TB flag that is set when we can guarantee that there is no active MVE predication, and a bool in the DisasContext. Subsequent patches will use this flag to generate improved code for some instructions. In most cases when the predication state changes we simply end the TB after that instruction. For the code called from vfp_access_check() that handles lazy state preservation and creating a new FP context, we can usually avoid having to try to end the TB because luckily the new value of the flag following the register changes in those sequences doesn't depend on any runtime decisions. We do have to end the TB if the guest has enabled lazy FP state preservation but not automatic state preservation, but this is an odd corner case that is not going to be common in real-world code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-4-peter.maydell@linaro.org
2021-09-21target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migrationPeter Maydell1-0/+13
Architecturally, for an M-profile CPU with the LOB feature the LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation enforces this everywhere, except that we don't check that it is true in incoming migration data. We're going to add come in gen_update_fp_context() which relies on the "always 4" property. Since this is TCG-only, we don't actually need to be robust to bogus incoming migration data, and the effect of it being wrong would be wrong code generation rather than a QEMU crash; but if it did ever happen somehow it would be very difficult to track down the cause. Add a check so that we fail the inbound migration if the FPDSCR.LTPSIZE value is incorrect. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
2021-09-21target/arm: Avoid goto_tb if we're trying to exit to the main loopPeter Maydell1-1/+33
Currently gen_jmp_tb() assumes that if it is called then the jump it is handling is the only reason that we might be trying to end the TB, so it will use goto_tb if it can. This is usually the case: mostly "we did something that means we must end the TB" happens on a non-branch instruction. However, there are cases where we decide early in handling an instruction that we need to end the TB and return to the main loop, and then the insn is a complex one that involves gen_jmp_tb(). For instance, for M-profile FP instructions, in gen_preserve_fp_state() which is called from vfp_access_check() we want to force an exit to the main loop if lazy state preservation is active and we are in icount mode. Make gen_jmp_tb() look at the current value of is_jmp, and only use goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-2-peter.maydell@linaro.org
2021-09-21hvf: arm: Add rudimentary PMC supportAlexander Graf1-0/+179
We can expose cycle counters on the PMU easily. To be as compatible as possible, let's do so, but make sure we don't expose any other architectural counters that we can not model yet. This allows OSs to work that require PMU support. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210916155404.86958-10-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-21arm: Add Hypervisor.framework build targetAlexander Graf3-0/+12
Now that we have all logic in place that we need to handle Hypervisor.framework on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we can build it. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> (x86 only) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210916155404.86958-9-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-21hvf: arm: Implement PSCI handlingAlexander Graf3-7/+139
We need to handle PSCI calls. Most of the TCG code works for us, but we can simplify it to only handle aa64 mode and we need to handle SUSPEND differently. This patch takes the TCG code as template and duplicates it in HVF. To tell the guest that we support PSCI 0.2 now, update the check in arm_cpu_initfn() as well. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210916155404.86958-8-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-21hvf: arm: Implement -cpu hostPeter Maydell5-6/+124
Now that we have working system register sync, we push more target CPU properties into the virtual machine. That might be useful in some situations, but is not the typical case that users want. So let's add a -cpu host option that allows them to explicitly pass all CPU capabilities of their host CPU into the guest. Signed-off-by: Alexander Graf <agraf@csgraf.de> Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210916155404.86958-7-agraf@csgraf.de [PMM: drop unnecessary #include line from .h file] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-21arm/hvf: Add a WFI handlerPeter Collingbourne3-3/+82
Sleep on WFI until the VTIMER is due but allow ourselves to be woken up on IPI. In this implementation IPI is blocked on the CPU thread at startup and pselect() is used to atomically unblock the signal and begin sleeping. The signal is sent unconditionally so there's no need to worry about races between actually sleeping and the "we think we're sleeping" state. It may lead to an extra wakeup but that's better than missing it entirely. Signed-off-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Alexander Graf <agraf@csgraf.de> Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210916155404.86958-6-agraf@csgraf.de [agraf: Remove unused 'set' variable, always advance PC on WFX trap, support vm stop / continue operations and cntv offsets] Signed-off-by: Alexander Graf <agraf@csgraf.de> Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: d6cb4dfe75a2f536f217d7075b750ece3acb1535.1631767043.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2-16/+16
The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but in fact it applies to M-mode and S-mode CSR too. Rename these macros to have the COUNTEREN_ prefix. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang1-1/+2
When virtual registers are swapped, mstatus.SD bit should also be backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept across the world switches. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210914013717.881430-1-frank.chang@sifive.com [ Changes by AF: - Convert variable to a uint64_t to fix clang error ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21docs/system/riscv: sifive_u: Update U-Boot instructionsBin Meng1-23/+26
In U-Boot v2021.07 release, there were 2 major changes for the SiFive Unleashed board support: - Board config name was changed from sifive_fu540_defconfig to sifive_unleashed_defconfig - The generic binman tool was used to generate the FIT image (combination of U-Boot proper, DTB and OpenSBI firmware) which make the existing U-Boot instructions out of date. Update the doc with latest instructions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911153431.10362-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang1-6/+6
Real PDMA doesn't set Control.error if there are 0 bytes to be transferred. The DMA transfer is still success. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x0 <= NextBytes = 0 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 55000000 00000000 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 40000001 55000000 00000000 00000000 ...@...U........ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan1-6/+10
Real PDMA is able to deal with non-multiple transaction size transactions. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x11000000 <= wsize = rsize = 1 (2^1 = 2 bytes) => mw.q 0x3000008 0x3 <= NextBytes = 3 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 11000000 00000003 00000000 ................ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 40000001 11000000 00000003 00000000 ...@............ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87345678 xV4. 84001000: 12345678 xV4. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210912130553.179501-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang1-0/+9
Real PDMA must have Control.claim bit to be set before Control.run bit is set to start any DMA transactions. Otherwise nothing will be transferred. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 (Channel 0 is not claimed) => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x2 <= NextBytes = 2 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000000 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 66000000 00000000 00000000 .......f........ 03000010: 00000000 00000000 00000000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang1-0/+19
Setting Control.claim clears all of the chanel's Next registers. This is effective only when Control.claim is set from 0 to 1. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel3-1/+124
We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-5-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-4-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel8-156/+339
The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-3-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel11-15/+15
We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-2-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>