summary refs log tree commit diff stats
path: root/scripts/qapi/source.py (unfollow)
Commit message (Collapse)AuthorFilesLines
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson11-0/+53
This hook may emit code at the beginning of the TB. Suggested-by: Jordan Niethe <jniethe5@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16fpu: Handle m68k extended precision denormals properlyRichard Henderson4-5/+66
Motorola treats denormals with explicit integer bit set as having unbiased exponent 0, unlike Intel which treats it as having unbiased exponent 1 (more like all other IEEE formats that have no explicit integer bit). Add a flag on FloatFmt to differentiate the behaviour. Reported-by: Keith Packard <keithp@keithp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16fpu: Add conversions between bfloat16 and [u]int8LIU Zhiwei2-0/+70
We missed these functions when upstreaming the bfloat16 support. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230531065458.2082-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Introduce do_st16_mmio_leNRichard Henderson1-30/+58
Split out int_st_mmio_leN, to be used by both do_st_mmio_leN and do_st16_mmio_leN. Move the locks down into the two functions, since each one now covers all accesses to once page. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Introduce do_ld16_mmio_beNRichard Henderson1-32/+59
Split out int_ld_mmio_beN, to be used by both do_ld_mmio_beN and do_ld16_mmio_beN. Move the locks down into the two functions, since each one now covers all accesses to once page. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Merge io_writex into do_st_mmio_leNRichard Henderson1-51/+29
Avoid multiple calls to io_prepare for unaligned acceses. One call to do_st_mmio_leN will never cross pages. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Merge io_readx into do_ld_mmio_beNRichard Henderson1-54/+30
Avoid multiple calls to io_prepare for unaligned acceses. One call to do_ld_mmio_beN will never cross pages. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1Richard Henderson1-2/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Merge cpu_transaction_failed into io_failedRichard Henderson1-20/+13
Push computation down into the if statements to the point the data is used. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16plugin: Simplify struct qemu_plugin_hwaddrRichard Henderson3-37/+17
Rather than saving MemoryRegionSection and offset, save phys_addr and MemoryRegion. This matches up much closer with the plugin api. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failedRichard Henderson1-8/+4
Since the introduction of CPUTLBEntryFull, we can recover the full cpu address space physical address without having to examine the MemoryRegionSection. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Split out io_prepare and io_failedRichard Henderson1-31/+44
These are common code from io_readx and io_writex. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16accel/tcg: Simplify tlb_plugin_lookupRichard Henderson3-70/+23
Now that we defer address space update and tlb_flush until the next async_run_on_cpu, the plugin run at the end of the instruction no longer has to contend with a flushed tlb. Therefore, delete SavedIOTLB entirely. Properly return false from tlb_plugin_lookup when we do not have a tlb match. Fixes a bug in which SavedIOTLB had stale data, because there were multiple i/o accesses within a single insn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16target/arm: Use tcg_gen_gvec_cmpi for compare vs 0Richard Henderson1-48/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230831030904.1194667-3-richard.henderson@linaro.org>
2023-09-16tcg: Add gvec compare with immediate and scalar operandRichard Henderson4-0/+206
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230831030904.1194667-2-richard.henderson@linaro.org>
2023-09-16tcg/loongarch64: Implement 128-bit load & storeJiajie Chen3-1/+62
If LSX is available, use LSX instructions to implement 128-bit load & store when MO_128 is required, otherwise use two 64-bit loads & stores. Signed-off-by: Jiajie Chen <c@jia.je> Message-Id: <20230908022302.180442-17-c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower rotli_vec to vrotriJiajie Chen2-1/+22
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-16-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower rotv_vec ops to LSXJiajie Chen2-1/+15
Lower the following ops: - rotrv_vec - rotlv_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-15-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector shift integer opsJiajie Chen2-1/+22
Lower the following ops: - shli_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-14-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen3-2/+12
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-13-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector shift vector opsJiajie Chen2-1/+25
Lower the following ops: - shlv_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-12-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector saturated opsJiajie Chen2-1/+33
Lower the following ops: - ssadd_vec - usadd_vec - sssub_vec - ussub_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-11-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector min max opsJiajie Chen2-1/+33
Lower the following ops: - smin_vec - smax_vec - umin_vec - umax_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-10-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower mul_vec to vmulJiajie Chen2-1/+9
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-9-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower neg_vec to vnegJiajie Chen2-1/+9
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-8-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector bitwise operationsJiajie Chen3-4/+50
Lower the following ops: - and_vec - andc_vec - or_vec - orc_vec - xor_vec - nor_vec - not_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-7-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen3-0/+63
Lower the following ops: - add_vec - sub_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-6-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen3-0/+67
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-5-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen11-12/+12
Pass vece to tcg_target_const_match() to allow correct interpretation of const args of vector ops. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230908022302.180442-4-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen5-2/+270
LSX support on host cpu is detected via hwcap. Lower the following ops to LSX: - dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-3-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Import LSX instructionsJiajie Chen1-1/+6018
Add opcodes and encoder functions for LSX. Generated from https://github.com/jiegec/loongarch-opcodes/tree/qemu-lsx. Signed-off-by: Jiajie Chen <c@jia.je> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-2-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15thunk: Delete checks for old host definitionsAkihiko Odaki1-2/+1
Alpha, IA-64, and PA-RISC hosts are no longer supported. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230808152314.102036-1-akihiko.odaki@daynix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15softmmu: Delete checks for old host definitionsAkihiko Odaki1-3/+0
PA-RISC host support is already removed with commit b1cef6d02f ("Drop remaining bits of ia64 host support"). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230810225922.21600-1-akihiko.odaki@daynix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15util: Delete checks for old host definitionsAkihiko Odaki1-12/+3
IA-64 and PA-RISC host support is already removed with commit b1cef6d02f ("Drop remaining bits of ia64 host support"). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230810225922.21600-1-akihiko.odaki@daynix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15accel/tcg: Fix the comment for CPUTLBEntryFullLIU Zhiwei2-10/+13
When memory region is ram, the lower TARGET_PAGE_BITS is not the physical section number. Instead, its value is always 0. Add comment and assert to make it clear. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230901060118.379-1-zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15accel/tcg: mttcg remove false-negative halted assertionNicholas Piggin1-7/+2
mttcg asserts that an execution ending with EXCP_HALTED must have cpu->halted. However between the event or instruction that sets cpu->halted and requests exit and the assertion here, an asynchronous event could clear cpu->halted. This leads to crashes running AIX on ppc/pseries because it uses H_CEDE/H_PROD hcalls, where H_CEDE sets self->halted = 1 and H_PROD sets other cpu->halted = 0 and kicks it. H_PROD could be turned into an interrupt to wake, but several other places in ppc, sparc, and semihosting follow what looks like a similar pattern setting halted = 0 directly. So remove this assertion. Reported-by: Ivan Warren <ivan@vmfacility.fr> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20230829010658.8252-1-npiggin@gmail.com> [rth: Keep the case label and adjust the comment.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-13tpm: fix crash when FD >= 1024 and unnecessary errors due to EINTRMarc-André Lureau1-9/+2
Replace select() with poll() to fix a crash when QEMU has a large number of FDs. Also use RETRY_ON_EINTR to avoid unnecessary errors due to EINTR. Cc: qemu-stable@nongnu.org Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2020133 Fixes: 56a3c24ffc ("tpm: Probe for connected TPM 1.2 or TPM 2") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2023-09-13target/i386: Call accel-agnostic x86_cpu_get_supported_cpuid()Philippe Mathieu-Daudé1-16/+16
x86_cpu_get_supported_cpuid() is generic and handles the different accelerators. Use it instead of kvm_arch_get_supported_cpuid(). That fixes a link failure introduced by commit 3adce820cf ("target/i386: Remove unused KVM stubs") when QEMU is configured as: $ ./configure --cc=clang \ --target-list=x86_64-linux-user,x86_64-softmmu \ --enable-debug We were getting: [71/71] Linking target qemu-x86_64 FAILED: qemu-x86_64 /usr/bin/ld: libqemu-x86_64-linux-user.fa.p/target_i386_cpu.c.o: in function `cpu_x86_cpuid': cpu.c:(.text+0x1374): undefined reference to `kvm_arch_get_supported_cpuid' /usr/bin/ld: libqemu-x86_64-linux-user.fa.p/target_i386_cpu.c.o: in function `x86_cpu_filter_features': cpu.c:(.text+0x81c2): undefined reference to `kvm_arch_get_supported_cpuid' /usr/bin/ld: cpu.c:(.text+0x81da): undefined reference to `kvm_arch_get_supported_cpuid' /usr/bin/ld: cpu.c:(.text+0x81f2): undefined reference to `kvm_arch_get_supported_cpuid' /usr/bin/ld: cpu.c:(.text+0x820a): undefined reference to `kvm_arch_get_supported_cpuid' /usr/bin/ld: libqemu-x86_64-linux-user.fa.p/target_i386_cpu.c.o:cpu.c:(.text+0x8225): more undefined references to `kvm_arch_get_supported_cpuid' follow clang: error: linker command failed with exit code 1 (use -v to see invocation) ninja: build stopped: subcommand failed. For the record, this is because '--enable-debug' disables optimizations (CFLAGS=-O0). While at this (un)optimization level GCC eliminate the following dead code (CPP output of mentioned build): static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { if ((0)) { *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); } else if (0) { *eax = 0; *ebx = 0; *ecx = 0; *edx = 0; } else { *eax = 0; *ebx = 0; *ecx = 0; *edx = 0; } Clang does not (see commit 2140cfa51d "i386: Fix build by providing stub kvm_arch_get_supported_cpuid()"). Cc: qemu-stable@nongnu.org Fixes: 3adce820cf ("target/i386: Remove unused KVM stubs") Reported-by: Kevin Wolf <kwolf@redhat.com> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230913093009.83520-4-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-13target/i386: Drop accel_uses_host_cpuid before x86_cpu_get_supported_cpuidPhilippe Mathieu-Daudé1-6/+4
x86_cpu_get_supported_cpuid() already checks for KVM/HVF accelerators, so it is not needed to manually check it via a call to accel_uses_host_cpuid() before calling it. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230913093009.83520-3-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-13target/i386: Check kvm_hyperv_expand_features() return valuePhilippe Mathieu-Daudé1-2/+2
In case more code is added after the kvm_hyperv_expand_features() call, check its return value (since it can fail). Fixes: 071ce4b03b ("i386: expand Hyper-V features during CPU feature expansion time") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230913093009.83520-2-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-13meson: Fix targetos match for illumos and Solaris.Jonathan Perkin2-3/+3
qemu 8.1.0 breaks on illumos platforms due to _XOPEN_SOURCE and others no longer being set correctly, leading to breakage such as: https://us-central.manta.mnx.io/pkgsrc/public/reports/trunk/tools/20230908.1404/qemu-8.1.0/build.log This is a result of meson conversion which incorrectly matches against 'solaris' instead of 'sunos' for uname. First time submitting a patch here, hope I did it correctly. Thanks. Signed-off-by: Jonathan Perkin <jonathan@perkin.org.uk> Message-ID: <ZPtdxtum9UVPy58J@perkin.org.uk> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-12hw/nvme: Avoid dynamic stack allocationPeter Maydell1-1/+1
Instead of using a variable-length array in nvme_map_prp(), allocate on the stack with a g_autofree pointer. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-09-12hw/nvme: Use #define to avoid variable length arrayPhilippe Mathieu-Daudé1-1/+1
In nvme_map_sgl() we create an array segment[] whose size is the 'const int SEG_CHUNK_SIZE'. Since this is C, rather than C++, a "const int foo" is not a true constant, it's merely a variable with a constant value, and so semantically segment[] is a variable-length array. Switch SEG_CHUNK_SIZE to a #define so that we can make the segment[] array truly fixed-size, in the sense that it doesn't trigger the -Wvla warning. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). [PMM: rebased (function has moved file), expand commit message based on discussion from previous version of patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-09-12tests/qtest/pflash: Clean up local variable shadowingPhilippe Mathieu-Daudé1-1/+1
Fix: tests/qtest/pflash-cfi02-test.c: In function ‘test_geometry’: tests/qtest/pflash-cfi02-test.c:409:22: warning: declaration of ‘byte_addr’ shadows a previous local [-Wshadow=compatible-local] 409 | uint64_t byte_addr = (uint64_t)i * c->sector_len[region]; | ^~~~~~~~~ tests/qtest/pflash-cfi02-test.c:342:14: note: shadowed declaration is here 342 | uint64_t byte_addr = 0; | ^~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230904162824.85385-4-philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-09-12kconfig: Add NVME to s390x machinesCédric Le Goater1-1/+1
We recently had issues with nvme devices on big endian platforms. Include their compilation on s390x to ease tests. Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20230828150148.120031-1-clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-09-12target/s390x: AP-passthrough for PV guestsSteffen Eiden5-0/+79
Enabling AP-passthrough(AP-pt) for PV-guest by using the new CPU features for PV-AP-pt of KVM. As usual QEMU first checks which CPU features are available and then sets them if available and selected by user. An additional check is done to verify that PV-AP can only be enabled if "regular" AP-pt is enabled as well. Note that KVM itself does not enforce this restriction. Reviewed-by: Michael Mueller <mimu@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Steffen Eiden <seiden@linux.ibm.com> Message-ID: <20230823142219.1046522-6-seiden@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-09-12target/s390x/kvm: Refactor AP functionalitiesSteffen Eiden1-7/+17
kvm_s390_set_attr() is a misleading name as it only sets attributes for the KVM_S390_VM_CRYPTO group. Therefore, rename it to kvm_s390_set_crypto_attr(). Add new functions ap_available() and ap_enabled() to avoid code duplication later. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Mueller <mimu@linux.ibm.com> Signed-off-by: Steffen Eiden <seiden@linux.ibm.com> Message-ID: <20230823142219.1046522-5-seiden@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-09-12linux-headers: Update to Linux v6.6-rc1Thomas Huth23-16/+351
This update contains the required header changes for the "target/s390x: AP-passthrough for PV guests" patch from Steffen Eiden. Message-ID: <20230912093432.180041-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-09-12s390x: do a subsystem reset before the unprotect on rebootJanosch Frank1-0/+10
Bound APQNs have to be reset before tearing down the secure config via s390_machine_unprotect(). Otherwise the Ultravisor will return a error code. So let's do a subsystem_reset() which includes a AP reset before the unprotect call. We'll do a full device_reset() afterwards which will reset some devices twice. That's ok since we can't move the device_reset() before the unprotect as it includes a CPU clear reset which the Ultravisor does not expect at that point in time. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Message-ID: <20230901114851.154357-1-frankja@linux.ibm.com> Tested-by: Viktor Mihajlovski <mihajlov@linux.ibm.com> Acked-by: Christian Borntraeger <borntraeger@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-09-12s390x/ap: fix missing subsystem reset registrationJanosch Frank1-0/+1
A subsystem reset contains a reset of AP resources which has been missing. Adding the AP bridge to the list of device types that need reset fixes this issue. Reviewed-by: Jason J. Herne <jjherne@linux.ibm.com> Reviewed-by: Tony Krowiak <akrowiak@linux.ibm.com> Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Fixes: a51b3153 ("s390x/ap: base Adjunct Processor (AP) object model") Message-ID: <20230823142219.1046522-2-seiden@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>