summary refs log tree commit diff stats
path: root/scripts/qapi/source.py (unfollow)
Commit message (Collapse)AuthorFilesLines
2024-09-09crypto: Introduce x509 utilsDorjoy Chowdhury3-0/+102
An utility function for getting fingerprint from X.509 certificate has been introduced. Implementation only provided using gnutls. Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> [DB: fixed missing gnutls_x509_crt_deinit in success path] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09crypto: Support SHA384 hash when using glibDorjoy Chowdhury1-1/+1
QEMU requires minimum glib version 2.66.0 as per the root meson.build file and per glib documentation[1] G_CHECKSUM_SHA384 is available since 2.51. [1] https://docs.gtk.org/glib/enum.ChecksumType.html Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09crypto: Define macros for hash algorithm digest lengthsDorjoy Chowdhury2-7/+15
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09crypto: use consistent error reporting pattern for unsupported cipher modesDaniel P. Berrangé1-4/+14
Not all paths in qcrypto_cipher_ctx_new() were correctly distinguishing between valid user input for cipher mode (which should report a user facing error), vs program logic errors (which should assert). Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09crypto: avoid leak of ctx when bad cipher mode is givenDaniel P. Berrangé1-2/+5
Fixes: Coverity CID 1546884 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09tests/unit: build pbkdf test on macOSDaniel P. Berrangé1-1/+1
Add CONFIG_DARWIN to the pbkdf test build condition, since we have a way to measure CPU time on this platform since commit bf98afc75efedf1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09tests/unit: always build the pbkdf crypto unit testDaniel P. Berrangé2-8/+9
The meson rules were excluding the pbkdf crypto test when gnutls was the crypto backend. It was then excluded again in #if statements in the test file. Rather than update these conditions, remove them all, and use the result of the qcrypto_pbkdf_supports() function to determine whether to skip test registration. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09crypto: check gnutls & gcrypt support the requested pbkdf hashDaniel P. Berrangé2-2/+2
Both gnutls and gcrypt can be configured to exclude support for certain algorithms via a runtime check against system crypto policies. Thus it is not sufficient to have a compile time test for hash support in their pbkdf implementations. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09crypto: run qcrypto_pbkdf2_count_iters in a new threadTiago Pasqualini1-7/+46
CPU time accounting in the kernel has been demonstrated to have a sawtooth pattern[1][2]. This can cause the getrusage system call to not be as accurate as we are expecting, which can cause this calculation to stall. The kernel discussions shows that this inaccuracy happens when CPU time gets big enough, so this patch changes qcrypto_pbkdf2_count_iters to run in a fresh thread to avoid this inaccuracy. It also adds a sanity check to fail the process if CPU time is not accounted. [1] https://lore.kernel.org/lkml/159231011694.16989.16351419333851309713.tip-bot2@tip-bot2/ [2] https://lore.kernel.org/lkml/20221226031010.4079885-1-maxing.lan@bytedance.com/t/#m1c7f2fdc0ea742776a70fd1aa2a2e414c437f534 Resolves: #2398 Signed-off-by: Tiago Pasqualini <tiago.pasqualini@canonical.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-09iotests: fix expected output from gnutlsDaniel P. Berrangé1-6/+6
Error reporting from gnutls was improved by: commit 57941c9c86357a6a642f9ee3279d881df4043b6d Author: Daniel P. Berrangé <berrange@redhat.com> Date: Fri Mar 15 14:07:58 2024 +0000 crypto: push error reporting into TLS session I/O APIs This has the effect of changing the output from one of the NBD tests. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-09-08hw/nubus/nubus-device: Range check 'slot' propertyPeter Maydell1-0/+7
The TYPE_NUBUS_DEVICE class lets the user specify the nubus slot using an int32 "slot" QOM property. Its realize method doesn't do any range checking on this value, which Coverity notices by way of the possibility that 'nd->slot * NUBUS_SUPER_SLOT_SIZE' might overflow the 32-bit arithmetic it is using. Constrain the slot value to be less than NUBUS_SLOT_NB (16). Resolves: Coverity CID 1464070 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240830173452.2086140-4-peter.maydell@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2024-09-08hw/m68k/mcf5208: Add URLs for datasheetsPeter Maydell1-0/+8
The datasheets for the SoC and board we model here are still available from the NXP website; add their URLs and titles for future reference. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-ID: <20240830173452.2086140-3-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2024-09-08hw/m68k/mcf5208: Avoid shifting off end of integerPeter Maydell1-1/+1
In m5208_sys_read(), we have a loop of n from 0 to 31, and we calculate (2u << n). For the n == 31 iteration this will shift off the top of the unsigned 32 bit integer. This is harmless, because we're going to stop the loop with n == 31 anyway, but we can avoid the error by using 64-bit arithmetic here. (The SDCS0 register is documented at https://www.nxp.com/docs/en/reference-manual/MCF5208RM.pdf section 18.4.5; we want the lower 5 bits to indicate the RAM size, where 31 == 4GB, 30 == 2GB, and so on down. As it happens, the layout of the mcf5208evb board memory map means it doesn't make sense to have more than 1GB of RAM in any case.) Resolves: Coverity CID 1547727 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-ID: <20240830173452.2086140-2-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2024-09-06tests/qtest: Bump timeout on ahci-testPeter Maydell1-0/+1
On my OpenBSD VM test system, the ahci-test sometimes hits its 60 second timeout. It has 75 subtests and allowing at least two seconds per subtest seems reasonable. Bump it to 150s. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240905165554.320577-3-peter.maydell@linaro.org
2024-09-06tests/qtest: Add missing qtest_quit() to stm32 testsPeter Maydell2-0/+4
In the dm163-test and stm32l4x5_usart-test, a couple of subtests are missing the qtest_quit() call. The effect of this is that on hosts other than Linux and FreeBSD the test will timeout after executing all the tests: 242/845 qemu:qtest+qtest-arm / qtest-arm/dm163-test TIMEOUT 60.04s 3 subtests passed 100/845 qemu:qtest+qtest-arm / qtest-arm/stm32l4x5_usart-test TIMEOUT 600.02s 5 subtests passed This happens because the qemu-system-arm binary which the test starts does not exit, and because it shares the stdout with the test binary, the overall meson test harness thinks the test is still running. On Linux and FreeBSD we have an extra safety net set up in qtest_spawn_qemu() which kills off any QEMU binary that ends up without a parent. This is intended for the case where QEMU crashed and didn't respond to a SIGTERM or polite request to quit, but it also sidestepped the problem in this case. However, OpenBSD doesn't have a PDEATHSIG equivalent, so we see the timeouts when running a 'make vm-build-openbsd' run. Add the missing qtest_quit() calls. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240905165554.320577-2-peter.maydell@linaro.org
2024-09-06hw/ufs: ufs descriptor read test implementedYoochan Jeong1-0/+153
New test function "ufstest_query_desc_request" added, which can check one's virtual UFS device can properly read and its descriptor data. (Writing descriptors are not implemented yet.) The testcases attempt to read all kinds of descriptors at least once, except for configuration descriptors (which are not implemented yet.) There are some testcases that are intended to make an error caused by an invalid index value or an invalid selector value. Signed-off-by: Yoochan Jeong <yc01.jeong@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2024-09-06hw/ufs: ufs attribute read/write test implementedYoochan Jeong1-0/+137
New test function "ufstest_query_attr_request" added, which can check one's virtual UFS device can properly read and write its attribute data. It tests if reading and writing attributes work properly. There are some testcases that are intended to make an error caused by writing an invalid value, allocating an invalid selector and permission issues. Signed-off-by: Yoochan Jeong <yc01.jeong@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2024-09-06hw/ufs: ufs flag read/write test implementedYoochan Jeong1-0/+83
New test function "ufstest_flag_request" added, which can check one's virtual UFS device can properly read and write its flag data. It tests if reading, setting, clearing and toggling flags work properly. There are some testcases that are intended to make an error caused by permission issues. Signed-off-by: Yoochan Jeong <yc01.jeong@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2024-09-06hw/ufs: minor bug fixes related to ufs-testYoochan Jeong3-9/+27
Minor bugs and errors related to ufs-test are resolved. Some permissions and code implementations that are not synchronized with the ufs spec are edited. Signed-off-by: Yoochan Jeong <yc01.jeong@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2024-09-06hw/ufs: add basic info of query response upiuKyoungrul Kim2-4/+10
Modify to fill the opcode, idn, index, selector information of all Query Response UPIU. because attr and flag operation of query response upiu need these information too. Signed-off-by: KyoungrulKim <k831.kim@samsung.com> Reviewed-by: Minwoo Im <minwoo.im@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2024-09-05platform-bus: fix refcount leakGao Shiyuan1-1/+4
memory_region_find() returns an MR which it is the caller's responsibility to unref, but platform_bus_map_mmio() was forgetting to do so, thus leaking the MR. Signed-off-by: Gao Shiyuan <gaoshiyuan@baidu.com> Message-id: 20240829131005.9196-1-gaoshiyuan@baidu.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-05hw/arm/boot: Explain why load_elf_hdr() error is ignoredPhilippe Mathieu-Daudé1-2/+6
If the file is not an ELF file, arm_setup_direct_kernel_boot() falls back to try it as a uimage or an AArch64 Image file or as last resort a bare raw binary. We can discard load_elf_hdr() error and silently return. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903144154.17135-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-05hw/arm/boot: Report error msg if loading elf/dtb failedChangbin Du1-0/+2
Print errors before exit. Do not exit silently. Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Changbin Du <changbin.du@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903133940.3447430-1-changbin.du@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-05hw/arm/xilinx_zynq: Enable Security ExtensionsSebastian Huber1-8/+0
The system supports the Security Extensions (core and GIC). This change is necessary to run tests which pass on the real hardware. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20240828005019.57705-1-sebastian.huber@embedded-brains.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-05target/arm: Correct names of VFP VFNMA and VFNMS insnsPeter Maydell2-10/+10
In vfp.decode we have the names of the VFNMA and VFNMS instructions the wrong way around. The architecture says that bit 6 is the 'op' bit, which is 1 for VFNMA and 0 for VFNMS, but we label these two lines of decode the other way around. This doesn't cause any user-visible problem because in the handling of these functions in translate-vfp.c we give VFNMA the behaviour specified for VFNMS and vice-versa, but it's confusing when reading the code. Switch the names of the VFP VFNMA and VFNMS instructions in the decode file and flip the behaviour also. NB: the instructions VFMA and VFMS *are* decoded with op=0 for VFMA and op=1 for VFMS; the confusion probably arose because we assumed VFNMA and VFNMS to be the same way around. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2536 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240830152156.2046590-1-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05hw/arm/sbsa-ref: Don't leak string in sbsa_fdt_add_gic_node()Peter Maydell1-9/+6
In sbsa_fdt_add_gic_node() we g_strdup_printf() two nodename strings, but only free one. Since the string is actually entirely constant and we don't make any use of printf's format-string operations, we can drop the g_strdup_printf() use entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20240822162323.706382-1-peter.maydell@linaro.org
2024-09-05hm/nvram/xlnx-versal-efuse-ctrl: Call register_finalize_blockPeter Maydell2-3/+4
The TYPE_XLNX_VERSAL_EFUSE_CTRL device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55f222b5b9d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294e9d8) (BuildId: 420 43d49e1139e3f3071b1f22fac1e3e7249c9a6) #1 0x7fbb10669c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55f222f90c5d in register_init_block hw/core/register.c:248:34 #3 0x55f222f916be in register_init_block32 hw/core/register.c:299:12 #4 0x55f223bbdd15 in efuse_ctrl_init hw/nvram/xlnx-versal-efuse-ctrl.c:718:9 #5 0x55f225b23391 in object_init_with_type qom/object.c:420:9 #6 0x55f225b0a66b in object_initialize_with_type qom/object.c:562:5 #7 0x55f225b0bf0d in object_new_with_type qom/object.c:782:5 #8 0x55f225b0bfe1 in object_new qom/object.c:797:12 #9 0x55f226309e0d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-7-peter.maydell@linaro.org
2024-09-05hw/misc/xlnx-versal-trng: Call register_finalize_blockPeter Maydell2-3/+4
The TYPE_XLNX_VERSAL_TRNG device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55842ec799d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294e9d8) (BuildId: 47496e53f3e779f1c7e9b82cbea07407152b498b) #1 0x7fe793c75c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55842f0aec5d in register_init_block hw/core/register.c:248:34 #3 0x55842f0af6be in register_init_block32 hw/core/register.c:299:12 #4 0x55842f801588 in trng_init hw/misc/xlnx-versal-trng.c:614:9 #5 0x558431c411a1 in object_init_with_type qom/object.c:420:9 #6 0x558431c2847b in object_initialize_with_type qom/object.c:562:5 #7 0x558431c29d1d in object_new_with_type qom/object.c:782:5 #8 0x558431c29df1 in object_new qom/object.c:797:12 #9 0x558432427c1d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-6-peter.maydell@linaro.org
2024-09-05hw/nvram/xlnx-zynqmp-efuse: Call register_finalize_blockPeter Maydell2-3/+11
The TYPE_XLNX_ZYNQMP_EFUSE device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55f3ff5839d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d9d8) (BuildId: 23cf931c66865a71b6cc4da95156d03bc106fa72) #1 0x7f3f31c6bc50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55f3ff9b8c5d in register_init_block hw/core/register.c:248:34 #3 0x55f3ff9b96be in register_init_block32 hw/core/register.c:299:12 #4 0x55f4005e5b25 in efuse_ctrl_init hw/nvram/xlnx-versal-efuse-ctrl.c:718:9 #5 0x55f40254afb1 in object_init_with_type qom/object.c:420:9 #6 0x55f40253228b in object_initialize_with_type qom/object.c:562:5 #7 0x55f402533b2d in object_new_with_type qom/object.c:782:5 #8 0x55f402533c01 in object_new qom/object.c:797:12 #9 0x55f402d31a2d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-5-peter.maydell@linaro.org
2024-09-05hw/nvram/xlnx-bbram: Call register_finalize_blockPeter Maydell2-3/+11
The TYPE_XLNX_BBRAM device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x5641518ca9d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d9d8) (BuildId: 4a6 18cb63d57d5a19ed45cfc262b08da47eaafe5) #1 0x7ff1aab31c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x564151cffc5d in register_init_block hw/core/register.c:248:34 #3 0x564151d006be in register_init_block32 hw/core/register.c:299:12 #4 0x56415293df75 in bbram_ctrl_init hw/nvram/xlnx-bbram.c:462:9 #5 0x564154891dc1 in object_init_with_type qom/object.c:420:9 #6 0x56415487909b in object_initialize_with_type qom/object.c:562:5 #7 0x56415487a93d in object_new_with_type qom/object.c:782:5 #8 0x56415487aa11 in object_new qom/object.c:797:12 #9 0x56415507883d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-4-peter.maydell@linaro.org
2024-09-05hw/misc/xlnx-versal-trng: Free s->prng in finalize, not unrealizePeter Maydell1-3/+3
The TYPE_XLNX_VERSAL_TRNG device creates s->prng with g_rand_new() in its init method, but it frees it in its unrealize method. This results in a leak in the QOM introspection "initialize-inspect-finalize" lifecycle: Direct leak of 2500 byte(s) in 1 object(s) allocated from: #0 0x55ec89eae9d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d9d8) (BuildId: 6d5 08874816cc47d17c8dd775e8f809ae520e8cb) #1 0x7f697018fc50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x7f6970197738 in g_rand_new_with_seed_array debian/build/deb/../../../glib/grand.c:202:17 #3 0x7f6970197816 in g_rand_new debian/build/deb/../../../glib/grand.c:286:10 #4 0x55ec8aa3656a in trng_init hw/misc/xlnx-versal-trng.c:624:15 #5 0x55ec8ce75da1 in object_init_with_type qom/object.c:420:9 #6 0x55ec8ce5d07b in object_initialize_with_type qom/object.c:562:5 #7 0x55ec8ce5e91d in object_new_with_type qom/object.c:782:5 #8 0x55ec8ce5e9f1 in object_new qom/object.c:797:12 #9 0x55ec8d65c81d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Move the free to finalize so it matches where we are initing s->prng. Since that's the only thing our unrealize method was doing, this essentially switches the whole function to be a finalize implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-3-peter.maydell@linaro.org
2024-09-05hw/misc/xlnx-versal-cfu: destroy fifo in finalizePeter Maydell1-0/+8
Since the TYPE_XNLX_VERSAL_CFU_FDRO device creates a FIFO in its instance_init method, we must destroy the FIFO in instance_finalize to avoid a memory leak for the QOM introspection "instantiate-examine-finalize" cycle: Direct leak of 8192 byte(s) in 1 object(s) allocated from: #0 0x55ec89eae7ee in malloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d7ee) (BuildId: 6d508874816cc47d17c8dd775e8f809ae520e8cb) #1 0x7f697018f738 in g_malloc debian/build/deb/../../../glib/gmem.c:128:13 #2 0x55ec8d98d98d in fifo8_create util/fifo8.c:27:18 #3 0x55ec8aa2a624 in fifo32_create /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/include/qemu/fifo32.h:35:5 #4 0x55ec8aa2a33c in cfu_fdro_init hw/misc/xlnx-versal-cfu.c:397:5 #5 0x55ec8ce75da1 in object_init_with_type qom/object.c:420:9 #6 0x55ec8ce5d07b in object_initialize_with_type qom/object.c:562:5 #7 0x55ec8ce5e91d in object_new_with_type qom/object.c:782:5 #8 0x55ec8ce5e9f1 in object_new qom/object.c:797:12 #9 0x55ec8d65c81d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240822162127.705879-2-peter.maydell@linaro.org
2024-09-05hw/arm/sbsa-ref: Use two-stage SMMUPeter Maydell1-0/+1
Now that our SMMU model supports enabling both stages of translation at once, we can enable this in the sbsa-ref board. Existing guest code that only programs stage 1 and doesn't care about stage 2 should continue to run with the same behaviour, but guests that do want to do nested SMMU configurations can now do so. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240816161350.3706332-5-peter.maydell@linaro.org
2024-09-05hw/arm/virt: Default to two-stage SMMU from virt-9.2Peter Maydell2-0/+9
Now that our SMMU model supports enabling both stages of translation at once, we can enable this in the virt board. This is no change in behaviour for guests, because if they simply ignore stage 2 and never configure it then it has no effect. For the usual backwards compatibility reasons we enable this only for machine types starting with 9.2. (Note that the SMMU is disabled by default on the virt board and is only created if the user passes the 'iommu=smmuv3' machine option.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240816161350.3706332-4-peter.maydell@linaro.org
2024-09-05hw/arm/smmuv3: Update comment documenting "stage" propertyPeter Maydell1-0/+1
When we added support for nested (stage 1 + stage 2) translation to the SMMU in commit 58377c363291d we forgot to update the comment that documents the valid values of the "stage" property. Add the new "nested" value to it. Fixes: 58377c363291d ("hw/arm/smmuv3: Support and advertise nesting") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240816161350.3706332-3-peter.maydell@linaro.org
2024-09-05hw: add compat machines for 9.2Cornelia Huck10-10/+77
Add 9.2 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240816161350.3706332-2-peter.maydell@linaro.org Message-id: 20240816103723.2325982-1-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-05accel/tcg: Remove dead code from rr_cpu_thread_fn()Peter Maydell1-3/+1
The main loop in rr_cpu_thread_fn() can never terminate, so the code at the end of the function to clean up the RCU subsystem is dead code. Replace it with g_assert_not_reached(). (This is different from the other cpu_thread_fn for e.g. MTTCG or for the KVM accelerator -- those can exit, if the vCPU they are responsible for is unplugged. But the RR cpu thread fn handles all CPUs in the system in a round-robin way, so even if one is unplugged it keeps looping.) Resolves: Coverity CID 1547782 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240815143634.3413679-1-peter.maydell@linaro.org
2024-09-05target/arm: Enable FEAT_EBF16 in the "max" CPUPeter Maydell3-3/+3
Now that we've implemented the required behaviour for FEAT_EBF16, we can enable it for the "max" CPU type, list it in our documentation, and delete a TODO comment about it being missing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Implement FPCR.EBF=1 semantics for bfdotadd()Peter Maydell1-3/+54
Implement the FPCR.EBF=1 semantics for bfdotadd() operations: * is_ebf() sets up fpst and fpst_odd * bfdotadd_ebf() implements the fused paired-multiply-and-add operation that we need The paired-multiply-and-add is similar to f16_dotadd() and we use the same trick here as in that function, but the inputs here are bfloat16 rather than float16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Prepare bfdotadd() callers for FEAT_EBF supportPeter Maydell3-65/+193
We use bfdotadd() in four callsites for various helper functions. Currently this all assumes that we have the FPCR.EBF=0 semantics. For FPCR.EBF=1 we will need to: * call a different routine to bfdotadd() because we need to do a fused multiply-add rather than separate multiply and add steps * use a different float_status that honours the FPCR rounding mode and denormal-flushing fields * pass in an extra float_status that has been set up to perform round-to-odd rounding To prepare for this, refactor all the callsites so that instead of for (...) { x = bfdotadd(...); } they are: float_status fpst, fpst_odd; if (is_ebf(env, &fpst, &fpst_odd)) { for (...) { x = bfdotadd_ebf(..., &fpst, &fpst_odd); } } else { for (...) { x = bfdotadd(..., &fpst); } } For the moment the is_ebf() function always returns false, sets up fpst for EBF=0 semantics and never sets up fpst_odd; bfdotadd_ebf() will assert if called. We'll fill in the handling for EBF=1 in the next commit. This change should be a zero-behaviour-change refactor. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Pass env pointer through to gvec_bfmmla helperPeter Maydell5-7/+8
Pass the env pointer through to the gvec_bfmmla helper, so we can use it to add support for FEAT_EBF16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Pass env pointer through to gvec_bfdot_idx helperPeter Maydell5-7/+22
Pass the env pointer through to the gvec_bfdot_idx helper, so we can use it to add support for FEAT_EBF16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Pass env pointer through to gvec_bfdot helperPeter Maydell5-7/+77
Pass the env pointer through to the gvec_bfdot helper, so we can use it to add support for FEAT_EBF16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Pass env pointer through to sme_bfmopa helperPeter Maydell3-5/+5
To implement the FEAT_EBF16 semantics, we are going to need the CPUARMState env pointer in every helper function which calls bfdotadd(). Pass the env pointer through from generated code to the sme_bfmopa helper. (We'll add the code that uses it when we've adjusted all the helpers to have access to the env pointer.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-05target/arm: Allow setting the FPCR.EBF bit for FEAT_EBF16Peter Maydell3-2/+12
FEAT_EBF16 adds one new bit to the FPCR floating point control register. Allow this bit to be read and written when the ID registers indicate the presence of the feature. Note that because this new bit is not in FPSCR_FPCR_MASK the bit is not visible in the AArch32 FPSCR, and FPSCR writes do not affect it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-04docs/system/i386: xenpvh: Add a basic descriptionEdgar E. Iglesias3-0/+51
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2024-09-04hw/i386/xen: Add a Xen PVH x86 machineEdgar E. Iglesias2-0/+122
Add a Xen PVH x86 machine based on the abstract PVH Machine. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2024-09-04hw/xen: pvh-common: Add support for creating PCIe/GPEXEdgar E. Iglesias2-0/+105
Add support for optionally creating a PCIe/GPEX controller. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2024-09-04hw/arm: xenpvh: Reverse virtio-mmio creation orderEdgar E. Iglesias1-1/+12
We've been creating the virtio-mmio devices in forwards order but since the qbus lists prepend (rather than append) entries, the virtio busses end up with decreasing base address order. Xen enables virtio-mmio nodes in forwards order so there's been a missmatch. So far, we've been working around this with an out-of-tree patch to Xen. This reverses the order making sure the virtio busses end up ordered with increasing base addresses avoiding the need to patch Xen. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
2024-09-04hw/arm: xenpvh: Rename xen_arm.c -> xen-pvh.cEdgar E. Iglesias2-1/+1
Rename xen_arm.c -> xen-pvh.c to better express that this is a PVH machine and to align with x86 HVM and future PVH machine filenames: hw/i386/xen/xen-hvm.c hw/i386/xen/xen-pvh.c (in preparation) No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>