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2021-10-29target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao1-4/+12
2021-10-29softfloat: add APIs to handle alternative sNaN propagation for fmax/fminChih-Min Chao3-8/+46
2021-10-29target/riscv: remove force HS exceptionJose Martins3-33/+1
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins1-20/+8
2021-10-28softmmu: fix for "after access" watchpointsPavel Dovgalyuk1-1/+1
2021-10-28softmmu: remove useless condition in watchpoint checkPavel Dovgalyuk1-21/+20
2021-10-28softmmu: fix watchpoint processing in icount modePavel Dovgalyuk1-4/+2
2021-10-28tcg/optimize: Propagate sign info for shiftingRichard Henderson1-3/+47
2021-10-28tcg/optimize: Propagate sign info for bit countingRichard Henderson1-1/+2
2021-10-28tcg/optimize: Propagate sign info for setcondRichard Henderson1-0/+2
2021-10-28tcg/optimize: Propagate sign info for logical operationsRichard Henderson1-0/+29
2021-10-28tcg/optimize: Optimize sign extensionsRichard Henderson1-21/+102
2021-10-28tcg/optimize: Use fold_xx_to_i for remRichard Henderson1-1/+5
2021-10-28tcg/optimize: Use fold_xi_to_x for divRichard Henderson1-1/+5
2021-10-28tcg/optimize: Use fold_xi_to_x for mulRichard Henderson1-1/+2
2021-10-28tcg/optimize: Use fold_xx_to_i for orcRichard Henderson1-0/+1
2021-10-28tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit valuesRichard Henderson1-19/+16
2021-10-28tcg: Extend call args using the correct opcodesRichard Henderson1-3/+3
2021-10-28Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson6-2/+120
2021-10-28Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson4-21/+9
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo1-0/+4
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev3-2/+57
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo5-0/+17
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo1-0/+7
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo1-0/+27
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo3-0/+298
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo1-0/+96
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo1-0/+2
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis1-2/+2
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis1-19/+1
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2-14/+1
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2-14/+1
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis2-0/+27
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2-2/+1
2021-10-27tcg/optimize: Sink commutative operand swapping into fold functionsRichard Henderson1-72/+70
2021-10-27tcg/optimize: Expand fold_addsub2_i32 to 64-bit opsRichard Henderson1-21/+44
2021-10-27tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multipliesRichard Henderson1-9/+35
2021-10-27tcg/optimize: Split out fold_masksRichard Henderson1-251/+294
2021-10-27tcg/optimize: Split out fold_ix_to_iRichard Henderson1-18/+10
2021-10-27tcg/optimize: Split out fold_xi_to_xRichard Henderson1-35/+26
2021-10-27tcg/optimize: Split out fold_sub_to_negRichard Henderson1-42/+47
2021-10-27tcg/optimize: Split out fold_to_notRichard Henderson1-72/+86
2021-10-27tcg/optimize: Add type to OptContextRichard Henderson1-59/+88
2021-10-27tcg/optimize: Split out fold_xi_to_iRichard Henderson1-18/+20
2021-10-27tcg/optimize: Split out fold_xx_to_xRichard Henderson1-15/+24
2021-10-27tcg/optimize: Split out fold_xx_to_iRichard Henderson1-17/+24
2021-10-27tcg/optimize: Split out fold_movRichard Henderson1-13/+14
2021-10-27tcg/optimize: Split out fold_dup, fold_dup2Richard Henderson1-22/+31
2021-10-27tcg/optimize: Split out fold_bswapRichard Henderson1-11/+16
2021-10-27tcg/optimize: Split out fold_count_zerosRichard Henderson1-14/+18