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2022-09-26s390x/pci: don't fence interpreted devices without MSI-XMatthew Rosato1-1/+5
Lack of MSI-X support is not an issue for interpreted passthrough devices, so let's let these in. This will allow, for example, ISM devices to be passed through -- but only when interpretation is available and being used. Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Message-Id: <20220902172737.170349-5-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-26s390x/pci: enable for load/store interpretationMatthew Rosato8-1/+137
If the ZPCI_OP ioctl reports that is is available and usable, then the underlying KVM host will enable load/store intepretation for any guest device without a SHM bit in the guest function handle. For a device that will be using interpretation support, ensure the guest function handle matches the host function handle; this value is re-checked every time the guest issues a SET PCI FN to enable the guest device as it is the only opportunity to reflect function handle changes. By default, unless interpret=off is specified, interpretation support will always be assumed and exploited if the necessary ioctl and features are available on the host kernel. When these are unavailable, we will silently revert to the interception model; this allows existing guest configurations to work unmodified on hosts with and without zPCI interpretation support, allowing QEMU to choose the best support model available. Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220902172737.170349-4-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-26s390x/pci: add routine to get host function handle from CLP infoMatthew Rosato2-16/+72
In order to interface with the underlying host zPCI device, we need to know its function handle. Add a routine to grab this from the vfio CLP capabilities chain. Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Message-Id: <20220902172737.170349-3-mjrosato@linux.ibm.com> [thuth: Replace free(info) with g_free(info)] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-26Update linux headers to v6.0-rc4Chenyi Qiang25-90/+538
commit 7e18e42e4b280c85b76967a9106a13ca61c16179 Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20220915091035.3897-3-chenyi.qiang@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-26configure: Add -Wno-gnu-variable-sized-type-not-at-endChenyi Qiang1-0/+1
A Linux headers update to v6.0-rc switches some definitions from GNU 'zero-length-array' extension to the C-standard-defined flexible array member. e.g. struct kvm_msrs { __u32 nmsrs; /* number of msrs in entries */ __u32 pad; - struct kvm_msr_entry entries[0]; + struct kvm_msr_entry entries[]; }; Those (unlike the GNU zero-length-array) have some extra restrictions like 'this must be put at the end of a struct', which clang build would complain about. e.g. the current code struct { struct kvm_msrs info; struct kvm_msr_entry entries[1]; } msr_data = { } generates the warning like: target/i386/kvm/kvm.c:2868:25: error: field 'info' with variable sized type 'struct kvm_msrs' not at the end of a struct or class is a GNU extension [-Werror,-Wgnu-variable-sized-type-not-at-end] struct kvm_msrs info; ^ In fact, the variable length 'entries[]' field in 'info' is zero-sized in GNU defined semantics, which can give predictable offset for 'entries[1]' in local msr_data. The local defined struct is just there to force a stack allocation large enough for 1 kvm_msr_entry, a clever trick but requires to turn off this clang warning. Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20220915091035.3897-2-chenyi.qiang@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-26target/s390x: support PRNO_TRNG instructionJason A. Donenfeld3-0/+32
In order for hosts running inside of TCG to initialize the kernel's random number generator, we should support the PRNO_TRNG instruction, backed in the usual way with the qemu_guest_getrandom helper. This is confirmed working on Linux 5.19. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-Id: <20220921100729.2942008-2-Jason@zx2c4.com> Reviewed-by: David Hildenbrand <david@redhat.com> [thuth: turn prno-trng off in avocado test to avoid breaking it] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-23target/s390x: support SHA-512 extensionsJason A. Donenfeld3-1/+240
In order to fully support MSA_EXT_5, we have to support the SHA-512 special instructions. So implement those. The implementation began as something TweetNacl-like, and then was adjusted to be useful here. It's not very beautiful, but it is quite short and compact, which is what we're going for. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [ restructure, add missing exception, add comments, fixup CPU model ] Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20220922153820.221811-1-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-23linux-user/host/s390: Add vector instructions to host_signal_write()Ilya Leoshkevich1-0/+25
The new noexec test fails on s390x with "unexpected SEGV". This test overwrites code using libc's memcpy(), which uses VSTL instruction. host_signal_write() does not recognize it, which causes SEGV to be incorrectly forwarded to the test. Add all vector instructions that write to memory to host_signal_write(). Fixes: ab12c95d3f19 ("target/s390x: Make translator stop before the end of a page") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20220920113907.334144-1-iii@linux.ibm.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-23s390x/tcg: Fix opcode for lzrfChristian Borntraeger1-1/+1
Fix the opcode for Load and Zero Rightmost Byte (32). Fixes: c2a5c1d718ea ("target/s390x: Implement load-and-zero-rightmost-byte insns") Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Cc: qemu-stable@nongnu.org Message-Id: <20220914105750.767697-1-borntraeger@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-21hw/microblaze: pass random seed to fdtJason A. Donenfeld1-0/+5
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This FDT node is part of the DT specification. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2022-09-21target/m68k: always call gen_exit_tb() after writes to SRMark Cave-Ayland1-0/+4
Any write to SR can change the security state so always call gen_exit_tb() when this occurs. In particular MacOS makes use of andiw/oriw in a few places to handle the switch between user and supervisor mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-21target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68KMark Cave-Ayland5-74/+75
The M68K_FEATURE_M68000 feature is misleading in that its name suggests the feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for all Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constants which define the features available for specific Motorola CPU models, rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K and add comments to clarify its usage. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-21target/m68k: Perform writback before modifying SRRichard Henderson1-3/+5
Writes to SR may change security state, which may involve a swap of %ssp with %usp as reflected in %a7. Finish the writeback of %sp@+ before swapping stack pointers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1206 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220913142818.7802-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-21target/m68k: Fix MACSR to CCRRichard Henderson1-2/+4
First, we were writing to the entire SR register, instead of only the flags portion. Second, we were not clearing C as per the documentation (X was cleared via the 0xf mask). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-21target/m68k: Implement atomic test-and-setRichard Henderson1-10/+30
This is slightly more complicated than cas, because tas is allowed on data registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220829051746.227094-1-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-20tests/docker: remove the Debian base imagesAlex Bennée6-74/+2
We no longer use these in any of our images. Clean-up the remaining comments and documentation that reference them and remove from the build. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-31-alex.bennee@linaro.org>
2022-09-20tests/docker: remove FROM qemu/ support from docker.pyAlex Bennée1-28/+10
We want to migrate from docker.py to building our images directly with docker/podman. Before we get there we need to make sure we don't re-introduce our layered builds so bug out if we see FROM qemu/ in a Dockerfile. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-30-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-toolchainAlex Bennée2-6/+3
Update to the latest stable Debian. While we are at it flatten into a single dockerfile as we do not need anything from the base image to build the toolchain. This is used to build both the nios and microblaze toolchains. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-29-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-hexagon-crossAlex Bennée1-7/+12
Update to the latest stable Debian. While we are at it flatten into a single dockerfile as we do not some of the extraneous packages from the base image to build the toolchain. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-28-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-loongarch-crossAlex Bennée2-4/+5
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. In this case it is a binary distribution of the toolchain anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-27-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-amd64-crossAlex Bennée4-18/+169
Now lcitool has support for building a x86_64 cross image we can use it for this. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-26-alex.bennee@linaro.org>
2022-09-20tests/lcitool: bump to latest versionAlex Bennée5-4/+5
We need this to be able to cleanly build the x86 cross images. There are a few minor updates triggered by lcitool-refresh including adding "libslirp" to the freebsd vars and opensuse-leap which will help when we finally drop the slirp submodule from QEMU. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-25-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-all-test-crossAlex Bennée3-7/+13
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We also need to ensure we install clang as it is used for those builds as well. It would be nice to port this to lcitool but for now this will do. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-24-alex.bennee@linaro.org>
2022-09-20tests/docker: flatten debian-riscv64-test-crossAlex Bennée3-6/+6
Flatten into a single dockerfile and update to match the rest of the test cross compile dockerfiles. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-23-alex.bennee@linaro.org>
2022-09-20Deprecate 32 bit big-endian MIPSAlex Bennée6-47/+26
It's becoming harder to maintain a cross-compiler to test this host architecture as the old stable Debian 10 ("Buster") moved into LTS which supports fewer architectures. For now: - mark it's deprecation in the docs - downgrade the containers to build TCG tests only - drop the cross builds from our CI Users with an appropriate toolchain and user-space can still take their chances building it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-22-alex.bennee@linaro.org>
2022-09-20gitlab-ci: update aarch32/aarch64 custom runner jobsAlex Bennée4-25/+24
The custom runner is now using 22.04 so we can drop our hacks to deal with broken libssh and glusterfs. The provisioning scripts will be updated in a separate commit. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-21-alex.bennee@linaro.org>
2022-09-20gitlab-ci/custom-runners: Disable -static-pie for ubuntu-20.04-aarch64Richard Henderson1-1/+3
The project has reached the magic size at which we see /usr/aarch64-linux-gnu/lib/libc.a(init-first.o): in function `__libc_init_first': (.text+0x10): relocation truncated to fit: R_AARCH64_LD64_GOTPAGE_LO15 against \ symbol `__environ' defined in .bss section in /usr/aarch64-linux-gnu/lib/libc.a(environ.o) /usr/bin/ld: (.text+0x10): warning: too many GOT entries for -fpic, please recompile with -fPIC The bug has been reported upstream, but in the meantime there is nothing we can do except build a non-pie executable. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220823210329.1969895-1-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-20-alex.bennee@linaro.org>
2022-09-20configure: explicitly set cflags for --disable-pieAlex Bennée1-0/+3
This is working around current limitation of Meson's handling of --disable-pie. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-19-alex.bennee@linaro.org>
2022-09-20hw/ppc/spapr: Fix code style problems reported by checkpatchBernhard Beschow1-2/+3
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20220919231720.163121-5-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-09-20hw/pci-host: pnv_phb{3, 4}: Fix heap out-of-bound access failureXuzhou Cheng2-0/+2
pnv_phb3_root_bus_info and pnv_phb4_root_bus_info are missing the instance_size initialization. This results in accessing out-of-bound memory when setting 'chip-id' and 'phb-id', and eventually crashes glib's malloc functionality with the following message: "qemu-system-ppc64: GLib: ../glib-2.72.3/glib/gmem.c:131: failed to allocate 3232 bytes" This issue was noticed only when running qtests with QEMU Windows 32-bit executable. Windows 64-bit, Linux 32/64-bit do not expose this bug though. Fixes: 9ae1329ee2fe ("ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge") Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20220920103159.1865256-29-bmeng.cn@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-09-20hw/ppc: spapr: Use qemu_vfree() to free spapr->htabXuzhou Cheng1-1/+1
spapr->htab is allocated by qemu_memalign(), hence we should use qemu_vfree() to free it. Fixes: c5f54f3e31bf ("pseries: Move hash page table allocation to reset time") Fixes: b4db54132ffe ("target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL"") Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220920103159.1865256-28-bmeng.cn@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-09-20tests/vm: Remove obsolete Fedora VM testThomas Huth2-192/+1
It's still based on Fedora 30 - which is not supported anymore by QEMU since years. Seems like nobody is using (and refreshing) this, and it's easier to test this via a container anyway, so let's remove this now. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220822175317.190551-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220914155950.804707-18-alex.bennee@linaro.org>
2022-09-20tests/docker: remove amd64 qemu/debian10 dependencyAlex Bennée1-1/+0
We missed removing this dependency when we flattened the build. Fixes 9e19fd7d4a (tests/docker: update debian-amd64 with lcitool) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-17-alex.bennee@linaro.org>
2022-09-20tests/docker: remove tricore qemu/debian10 dependencyAlex Bennée2-2/+0
We missed removing this dependency when we flattened the build. Fixes: 39ce923732 (gitlab: enable a very minimal build with the tricore container) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-16-alex.bennee@linaro.org>
2022-09-20tests/docker: flatten debian-powerpc-test-crossAlex Bennée3-7/+7
Flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-15-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-sparc64-crossAlex Bennée3-7/+7
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-14-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-sh4-crossAlex Bennée3-7/+7
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-13-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-mips64-crossAlex Bennée3-7/+7
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-12-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-m68k-crossAlex Bennée3-7/+7
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-11-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-hppa-crossAlex Bennée3-7/+7
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-10-alex.bennee@linaro.org>
2022-09-20tests/docker: update and flatten debian-alpha-crossAlex Bennée3-7/+7
Update to the latest stable Debian. While we are at it flatten into a single dockerfile. We really don't need the rest of the stuff from the QEMU base image just to compile test images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-9-alex.bennee@linaro.org>
2022-09-20tests/avocado: reduce the default timeout to 120sAlex Bennée1-1/+1
We should be aiming to keep our tests under 2 minutes so lets reduce the default timeout to that. Tests that we know take longer should explicitly set a longer timeout. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-8-alex.bennee@linaro.org>
2022-09-20tests/avocado: split the AST2x00Machine classesAlex Bennée1-0/+18
The SDK tests take a lot longer to run and hence need a longer timeout. As they run well over the 60 second maximum for CI lets also disable them for CI as well. I suspect they also suffer from the inability to detect the login prompt due to no newlines being processed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-7-alex.bennee@linaro.org>
2022-09-20tests/avocado: add explicit timeout for ppc64le TCG testsAlex Bennée1-0/+2
We don't want to rely on the soon to be reduced default time. These tests are still slow for something we want to run in CI though. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-6-alex.bennee@linaro.org>
2022-09-20tests/avocado: add explicit timeout for s390 TCG testsAlex Bennée1-0/+2
We don't want to rely on the soon to be reduced default time. These tests are still slow for something we want to run in CI though. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220914155950.804707-5-alex.bennee@linaro.org>
2022-09-20tests/avocado: add explicit timeout for Aarch64 TCG testsAlex Bennée1-0/+1
We don't want to rely on the soon to be reduced default time. These tests are still slow for something we want to run in CI though. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-4-alex.bennee@linaro.org>
2022-09-20tests/avocado/boot_linux_console: Fix the test_aarch64_xlnx_versal_virt testThomas Huth1-3/+3
The assets that this test tries to download have been removed from the server. Update to a newer version to get it working again. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220829080940.110831-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220914155950.804707-3-alex.bennee@linaro.org>
2022-09-20gitlab: reduce targets in cross_user_build_jobAlex Bennée1-1/+4
We already limit the scope of the cross system build to reduce the cross build times. With the recent addition of more targets we are also running into timeout issues for some of the cross user builds. I've selected a few of those linux-user targets which are less likely to be in common use as distros don't have pre-built rootfs for them. I've also added the same CROSS_SKIP_TARGETS variable as is occasionally used to further limit cross system builds. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220914155950.804707-2-alex.bennee@linaro.org>
2022-09-20target/ppc: Clear fpstatus flags on helpers missing itVíctor Colombo1-11/+26
In ppc emulation, exception flags are not cleared at the end of an instruction. Instead, the next instruction is responsible to clear it before its emulation. However, some helpers are not doing it, causing an issue where the previously set exception flags are being used and leading to incorrect values being set in FPSCR. Fix this by clearing fp_status before doing the instruction 'real' work for the following helpers that were missing this behavior: - VSX_CVT_INT_TO_FP_VECTOR - VSX_CVT_FP_TO_FP - VSX_CVT_FP_TO_INT_VECTOR - VSX_CVT_FP_TO_INT2 - VSX_CVT_FP_TO_INT - VSX_CVT_FP_TO_FP_HP - VSX_CVT_FP_TO_FP_VECTOR - VSX_CMP - VSX_ROUND - xscvqpdp - xscvdpsp[n] Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-09-20target/ppc: Zero second doubleword of VSR registers for FPR insnsVíctor Colombo1-0/+8
FPR register are mapped to the first doubleword of the VSR registers. Since PowerISA v3.1, the second doubleword of the target register must be zeroed for FP instructions. This patch does it by writting 0 to the second dw everytime the first dw is being written using set_fpr. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>