summary refs log tree commit diff stats
path: root/scripts/render_block_graph.py (unfollow)
Commit message (Expand)AuthorFilesLines
2022-01-21python/qmp: switch qom tools to AQMPJohn Snow3-8/+11
2022-01-21python/qmp: switch qemu-ga-client to AQMPJohn Snow1-11/+11
2022-01-21python/qemu-ga-client: don't use deprecated CLI syntax in usage commentJohn Snow1-1/+1
2022-01-21python/aqmp: rename AQMPError to QMPErrorJohn Snow6-21/+21
2022-01-21python/aqmp: add SocketAddrT to package rootJohn Snow1-1/+9
2022-01-21python/aqmp: copy type definitions from qmpJohn Snow2-8/+30
2022-01-21python/aqmp: handle asyncio.TimeoutError on execute()John Snow1-2/+6
2022-01-21python/aqmp: add __del__ method to legacy interfaceJohn Snow1-0/+18
2022-01-21python/aqmp: fix docstring typoJohn Snow1-1/+1
2022-01-21python: use avocado's "new" runnerJohn Snow1-1/+1
2022-01-21python: pin setuptools below v60.0.0John Snow2-0/+3
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei1-4/+4
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei2-6/+25
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei1-0/+10
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei1-10/+15
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei1-2/+2
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei1-1/+0
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei2-2/+10
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei5-6/+19
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei3-23/+16
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei5-69/+21
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei1-24/+8
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei5-0/+68
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei2-5/+10
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei1-0/+3
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei2-24/+55
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei1-3/+19
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Create xl field in envLIU Zhiwei5-32/+46
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei4-9/+27
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei2-6/+2
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei3-9/+6
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei2-8/+23
2022-01-21roms/opensbi: Remove ELF imagesAnup Patel5-6/+0
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel2-4/+2
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel4-28/+52
2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang1-0/+3
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang1-0/+18
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang1-0/+21
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang1-2/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang5-4/+7
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang1-3/+6
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang1-7/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang1-1/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang1-10/+31
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang1-2/+25