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2025-01-16tcg/riscv: Use BEXTI for single-bit extractionsRichard Henderson2-3/+16
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250102181601.1421059-3-richard.henderson@linaro.org>
2025-01-16util/cpuinfo-riscv: Detect ZbsRichard Henderson2-4/+19
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250102181601.1421059-2-richard.henderson@linaro.org>
2025-01-16tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}Richard Henderson15-65/+35
Make deposit "unconditional" in the sense that the opcode is always present. Rely instead on TCG_TARGET_deposit_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}Richard Henderson14-70/+8
Make extract and sextract "unconditional" in the sense that the opcodes are always present. Rely instead on TCG_TARGET_HAS_{s}extract_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/tci: Remove assertions for deposit and extractRichard Henderson1-18/+2
We already have these assertions during opcode creation. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/tci: Provide TCG_TARGET_{s}extract_validRichard Henderson1-0/+3
Trivially mirrors TCG_TARGET_HAS_{s}extract_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/sparc64: Use SRA, SRL for {s}extract_i64Richard Henderson2-4/+20
Extracts which abut bit 32 may use 32-bit shifts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2-2/+57
Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64Richard Henderson2-21/+19
Extracts which abut bit 32 may use 32-bit shifts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2-4/+69
Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2-2/+44
Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2-7/+52
Accept AND, ext32u, ext32s extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2-4/+45
Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/arm: Add full [US]XT[BH] into {s}extractRichard Henderson2-8/+67
The armv6 uxt and sxt opcodes have a 2-bit rotate field which supports extractions from ofs = {0,8,16,24}. Special case ofs = 0, len <= 8 as AND. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/aarch64: Expand extract with offset 0 with andiRichard Henderson1-1/+6
We're about to change canonicalization of masks as extract instead of and. Retain the andi expansion here. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/aarch64: Provide TCG_TARGET_{s}extract_validRichard Henderson1-0/+3
Trivially mirrors TCG_TARGET_HAS_{s}extract_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson5-36/+107
Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/i386: Handle all 8-bit extensions for i686Richard Henderson1-4/+19
When we generalize {s}extract_i32, we'll lose the specific register constraints on ext8u and ext8s. It's just as easy to emit a couple of insns instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/mips: Expand bswap unconditionallyRichard Henderson1-4/+4
We always provide bswap subroutines, whether they are optimized using mips32r2 when available or not. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Replace IMPLVEC with TCG_OPF_VECTORRichard Henderson6-79/+76
This is now a direct replacement. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Drop implementation checks from tcg-opc.hRichard Henderson1-171/+147
Now that we use a functional interface to query whether the opcode is supported, we can drop the TCG_OPF_NOT_PRESENT bit mapping from TCG_TARGET_HAS_foo in tcg-opc.h Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Remove TCG_OPF_64BITRichard Henderson2-13/+11
This flag is no longer used. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Add TCGType argument to tcg_out_opRichard Henderson11-24/+19
Pass TCGOp.type to the output function. For aarch64 and tci, use this instead of testing TCG_OPF_64BIT. For s390x, use this instead of testing INDEX_op_deposit_i64. For i386, use this to initialize rexw. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Pass type and flags to tcg_target_op_defRichard Henderson11-12/+22
Allow the backend to make constraint choices based on more parameters. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputsRichard Henderson2-7/+4
The br, mb, goto_tb and exit_tb opcodes do not have register operands, only constants, flags, or labels. Remove the special case in opcode_args_ct by including TCG_OPF_NOT_PRESENT in the flags for these opcodes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Validate op supported in opcode_args_ctRichard Henderson1-0/+4
We should have checked that the op is supported before emitting it. The backend cannot be expected to have a constraint set for unsupported ops. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Constify tcg_op_defsRichard Henderson3-3/+3
Now that we're no longer assigning to TCGOpDef.args_ct, we can make the array constant. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Remove args_ct from TCGOpDefRichard Henderson3-43/+38
Introduce a new function, opcode_args_ct, to look up the argument set for an opcode. We lose the ability to assert the correctness of the map from TCGOpcode to constraint sets at startup, but we can still validate at runtime upon lookup. Rename process_op_defs to process_constraint_sets, as it now does nothing to TCGOpDef. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Reorg process_op_defsRichard Henderson2-147/+140
Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint arrays based on those. Only afterward process the TCGOpcodes and share those TCGArgConstraint arrays. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Change have_vec to has_type in tcg_op_supportedRichard Henderson1-23/+43
Test each vector type, not just lumping them all together. Add tests for I32 (always true) and I64 (64-bit hosts). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Use C_NotImplemented in tcg_target_op_defRichard Henderson11-14/+16
Return C_NotImplemented instead of asserting for opcodes not implemented by the backend. For now, the assertion moves to process_op_defs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Split out tcg-target-mo.hRichard Henderson22-32/+136
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Only include 'tcg-has.h' when necessaryRichard Henderson9-4/+8
TCG_TARGET_HAS_* definitions don't need to be exposed by "tcg/tcg.h". Only include 'tcg-has.h' when necessary. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-15-philmd@linaro.org>
2025-01-16tcg: Include 'tcg-target-has.h' once in 'tcg-has.h'Richard Henderson11-20/+2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-14-philmd@linaro.org>
2025-01-16tcg/tci: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-74/+84
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-13-philmd@linaro.org>
2025-01-16tcg/sparc64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-76/+88
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-12-philmd@linaro.org>
2025-01-16tcg/s390x: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-113/+125
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-11-philmd@linaro.org>
2025-01-16tcg/riscv: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-101/+113
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-10-philmd@linaro.org>
2025-01-16tcg/ppc: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-113/+125
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-9-philmd@linaro.org>
2025-01-16tcg/mips: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-111/+123
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-8-philmd@linaro.org>
2025-01-16tcg/loongarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-101/+114
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-7-philmd@linaro.org>
2025-01-16tcg/i386: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-128/+140
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-6-philmd@linaro.org>
2025-01-16tcg/arm: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-73/+86
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-5-philmd@linaro.org>
2025-01-16tcg/aarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2-108/+120
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-4-philmd@linaro.org>
2025-01-16tcg: Extract default TCG_TARGET_HAS_foo definitions to 'tcg-has.h'Richard Henderson2-104/+116
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-3-philmd@linaro.org>
2025-01-16tcg/ppc: Remove TCGPowerISA enumRichard Henderson1-8/+0
Left-over from commit 623d7e3551a ("util: Add cpuinfo-ppc.c"). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-2-philmd@linaro.org>
2025-01-16tcg: Move fallback tcg_can_emit_vec_op out of lineRichard Henderson2-7/+4
Don't reference TCG_TARGET_MAYBE_vec in a public header. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.incRichard Henderson2-7/+4
Now that tcg-target-opc.h.inc is unconditional, we can move these out of the generic header. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Rename tcg-target.opc.h to tcg-target-opc.h.incRichard Henderson11-3/+4
In addition, add empty files for mips, sparc64 and tci. Make the include unconditional within tcg-opc.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELSRichard Henderson23-286/+216
Make these features unconditional, as they're used by most tcg backends anyway. Merge tcg-ldst.c.inc and tcg-pool.c.inc into tcg.c and mark some of the functions unused, so that when the features are not used we won't get Werrors. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>