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2017-01-27arm_gicv3: Fix broken logic in ELRSR calculationPeter Maydell1-1/+1
Fix a broken expression in the calculation of ELRSR register bits: instead of "(lr & ICH_LR_EL2_HW) == 1" we want to check for != 0, because the HW bit is not bit 0 so a test for == 1 is always false. Fixes: https://bugs.launchpad.net/bugs/1658506 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 1485255993-6322-1-git-send-email-peter.maydell@linaro.org
2017-01-27hw/char/exynos4210_uart: Drop unused local variable frame_sizePeter Maydell1-5/+1
The frame_size local variable in exynos4210_uart_update_parameters() is calculated but never used (and has been this way since the device was introduced in commit e5a4914efc7). The qemu_chr_fe_ioctl() doesn't need this information (if it really wanted it it could calculate it from the parity/data_bits/stop_bits), so just drop the variable entirely. Fixes: https://bugs.launchpad.net/bugs/1655702 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1484589515-26353-1-git-send-email-peter.maydell@linaro.org
2017-01-27arm: stellaris: make MII accesses complete immediatelyMichael Davidsaver1-1/+4
When the guest attempts to start an MII register access via the MCTL register, clear the START bit, so that when the guest reads it back the register transaction will be signalled as having completed. This avoids the guest spinning as it polls the START bit waiting for it to clear (which it previously never would). The MII registers themselves still aren't implemented, but at least we can avoid guests spending quite so much time busy waiting. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1484938222-1423-1-git-send-email-peter.maydell@linaro.org [PMM: expand commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: R14 should reset to 0xffffffffPeter Maydell1-0/+3
For M profile (unlike A profile) the reset value of R14 is specified as 0xffffffff. (The rationale is that this is an illegal exception return value, so if guest code tries to return to it it will result in a helpful exception.) Registers r0 to r12 and the flags are architecturally UNKNOWN on reset, so we leave those at zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-11-git-send-email-peter.maydell@linaro.org
2017-01-27armv7m: FAULTMASK should be 0 on resetMichael Davidsaver1-4/+6
For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK. QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the I bit) we have to clear these to undo the A profile default of 1. Update the comment accordingly and move it so that it's closer to the code it's referring to. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-10-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message, moved comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: Honour CCR.USERSETMPENDMichael Davidsaver1-1/+4
The CCR.USERSETMPEND bit has to be set to permit unprivileged code to write to the Software Triggered Interrupt register; honour this bit rather than letting any code write to the register. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-9-git-send-email-peter.maydell@linaro.org [PMM: Tweak commit message, comment, phrasing of condition] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: Report no-coprocessor faults correctlyPeter Maydell4-0/+14
For v7M attempts to access a nonexistent coprocessor are reported differently from plain undefined instructions (as UsageFaults of type NOCP rather than type UNDEFINSTR). Split them out into a new EXCP_NOCP so we can report the FSR value correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-8-git-send-email-peter.maydell@linaro.org
2017-01-27armv7m: set CFSR.UNDEFINSTR on undefined instructionsMichael Davidsaver1-0/+1
When we take an exception for an undefined instruction, set the appropriate CFSR bit. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-7-git-send-email-peter.maydell@linaro.org [PMM: tweaked commit message, comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: honour CCR.STACKALIGN on exception entryMichael Davidsaver1-4/+2
The CCR.STACKALIGN bit controls whether the CPU is supposed to force 8-alignment of the stack pointer on entry to the exception handler. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1485285380-10565-6-git-send-email-peter.maydell@linaro.org [PMM: commit message and comment tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFARMichael Davidsaver1-10/+32
Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and MMFAR. For the moment these simply read as written (with some basic handling of RAZ/WI bits and W1C semantics). Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-5-git-send-email-peter.maydell@linaro.org [PMM: drop warning about setting unimplemented CCR bits; tweak commit message; add DFSR] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFARPeter Maydell3-2/+69
Add the structure fields, VMState fields, reset code and macros for the v7M system control registers CCR, CFSR, HFSR, DFSR, MMFAR and BFAR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-4-git-send-email-peter.maydell@linaro.org
2017-01-27armv7m_nvic: keep a pointer to the CPUMichael Davidsaver1-6/+5
Many NVIC operations access the CPU state, so store a pointer in struct nvic_state rather than fetching it via qemu_get_cpu() every time we need it. As with the arm_gicv3_common code, we currently just call qemu_get_cpu() in the NVIC's realize method, but in future we might want to use a QOM property to pass the CPU to the NVIC. This imposes an ordering requirement that the CPU is realized before the NVIC, but that is always true since both are dealt with in armv7m_init(). Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-3-git-send-email-peter.maydell@linaro.org [PMM: Use qemu_get_cpu(0) rather than first_cpu; expand commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27target/arm: Drop IS_M() macroPeter Maydell3-8/+2
We only use the IS_M() macro in two places, and it's a bit of a namespace grab to put in cpu.h. Drop it in favour of just explicitly calling arm_feature() in the places where it was used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-2-git-send-email-peter.maydell@linaro.org
2017-01-27pflash_cfi01: fix per-device sector length in CFI tablePeter Maydell2-5/+21
For configurations of the pflash_cfi01 device which set it up with a device-width not equal to the width (ie where we are emulating multiple narrow flash devices wired up in parallel), we were giving incorrect values in the CFI data table: (1) the sector length entry should specify the sector length for a single device, not the length for the overall collection of devices (2) the number of blocks per device must not be divided by the number of devices because the resulting device size would not match the overall size (3) this then means that the overall write block size must be modified depending on the number of devices because the entry is per device and when the guest writes into the flash it calculates the write size by using the CFI entry (write size per device) multiplied by the number of chips. (It would alternatively be possible to modify the write block size in the CFI table (currently hardcoded at 2048) and leave the overall write block size alone.) This commit corrects these bugs, and adds a hw-compat property to retain the old behaviour on 2.8 and earlier versions. (The only board we have which uses this sort of flash config and has machine versioning is the "virt" board -- the PC uses a single flash device and so behaviour is unaffected whether using old-multiple-chip-handling or not.) Here is a configuration example from the vexpress board: VEXPRESS_FLASH_SIZE = 64M VEXPRESS_FLASH_SECT_SIZE 256K num-blocks = VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE = 256 sector-length = 256K width = 4 device-width = 2 The code will fill the CFI entry with the following entries: num-blocks = 256 sector-length = 128K writeblock_size = 2048 This results in two chips, each with 256 * 128K = 32M device size and a write block size of 2048. A sector erase will be sent to both chips, thus 256K must be erased. When the guest sends a block write command, it will write 4096 bytes data at once (2048 per device). Signed-off-by: David Engraf <david.engraf@sysgo.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: cleaned up and expanded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: Clear FAULTMASK on return from non-NMI exceptionsMichael Davidsaver1-1/+6
FAULTMASK must be cleared on return from all exceptions other than NMI. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-7-git-send-email-peter.maydell@linaro.org
2017-01-27armv7m: Fix reads of CONTROL register bit 1Michael Davidsaver4-17/+32
The v7m CONTROL register bit 1 is SPSEL, which indicates the stack being used. We were storing this information not in v7m.control but in the separate v7m.other_sp structure field. Unfortunately, the code handling reads of the CONTROL register didn't take account of this, and so if SPSEL was updated by an exception entry or exit then a subsequent guest read of CONTROL would get the wrong value. Using a separate structure field doesn't really gain us anything in efficiency, so drop this unnecessary complexity in favour of simply storing all the bits in v7m.control. This is a migration compatibility break for M profile CPUs only. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-6-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message; use deposit32(); use FIELD to define constants for masking and shifting of CONTROL register fields ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27hw/registerfields.h: Pull FIELD etc macros out of hw/register.hPeter Maydell2-46/+61
hw/register.h provides macros like FIELD which make it easy to define shift, mask and length constants for the fields within a register. Unfortunately register.h also includes a lot of other things, some of which will only compile in the softmmu build. Pull the FIELD macro and friends out into a separate header file, so they can be used in places like target/arm files which also get built in the user-only configs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-5-git-send-email-peter.maydell@linaro.org
2017-01-27armv7m: Explicit error for bad vector tableMichael Davidsaver1-1/+25
Give an explicit error and abort when a load from the vector table fails. Architecturally this should HardFault (which will then immediately fail to load the HardFault vector and go into Lockup). Since we don't model Lockup, just report this guest error via cpu_abort(). This is more helpful than the previous behaviour of reading a zero, which is the address of the reset stack pointer and not a sensible location to jump to. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-4-git-send-email-peter.maydell@linaro.org [PMM: expanded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: Replace armv7m.hack with unassigned_access handlerMichael Davidsaver3-14/+34
For v7m we need to catch attempts to execute from special addresses at 0xfffffff0 and above. Previously we did this with the aid of a hacky special purpose lump of memory in the address space and a check in translate.c for whether we were translating code at those addresses. We can implement this more cleanly using a CPU unassigned access handler which throws the exception if the unassigned access is for one of the special addresses. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-3-git-send-email-peter.maydell@linaro.org [PMM: * drop the deletion of the "don't interrupt if PC is magic" code in arm_v7m_cpu_exec_interrupt() -- this is still required * don't generate an exception for unassigned accesses which aren't to the magic address -- although doing this is in theory correct in practice it will break currently working guests which rely on the RAZ/WI behaviour when they touch devices which we haven't modelled. * trigger EXCP_EXCEPTION_EXIT on is_exec, not !is_write ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27armv7m: MRS/MSR: handle unprivileged accessMichael Davidsaver1-42/+37
The MRS and MSR instruction handling has a number of flaws: * unprivileged accesses should only be able to read CONTROL and the xPSR subfields, and only write APSR (others RAZ/WI) * privileged access should not be able to write xPSR subfields other than APSR * accesses to unimplemented registers should log as guest errors, not abort QEMU Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1484937883-1068-2-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-27aspeed/smc: handle dummy bytes when doing fast reads in command modeCédric Le Goater1-0/+21
When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control Register and needs to be modeled using fake transfers to the flash module. This only supports command mode. User mode requires more work and a possible extension of the m25p80 device model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Marcin Krzemiński <mar.krzeminski@gmail.com> Message-id: 1484751701-2646-1-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-26io: fix possible double free of task error objectDaniel P. Berrange2-1/+4
If a QIOTask has an error set and the calling code uses qio_task_propagate_error() to steal the reference to that Error object, the task would not clear its own reference. This would lead to a double-free when qio_task_free runs, if the caller had (correctly) freed the Error object they now owned. Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2017-01-26aio-posix: honor is_external in AioContext pollingStefan Hajnoczi1-1/+2
AioHandlers marked ->is_external must be skipped when aio_node_check() fails. bdrv_drained_begin() needs this to prevent dataplane from submitting new I/O requests while another thread accesses the device and relies on it being quiesced. This patch fixes the following segfault: Program terminated with signal SIGSEGV, Segmentation fault. #0 0x00005577f6127dad in bdrv_io_plug (bs=0x5577f7ae52f0) at qemu/block/io.c:2650 2650 bdrv_io_plug(child->bs); [Current thread is 1 (Thread 0x7ff5c4bd1c80 (LWP 10917))] (gdb) bt #0 0x00005577f6127dad in bdrv_io_plug (bs=0x5577f7ae52f0) at qemu/block/io.c:2650 #1 0x00005577f6114363 in blk_io_plug (blk=0x5577f7b8ba20) at qemu/block/block-backend.c:1561 #2 0x00005577f5d4091d in virtio_blk_handle_vq (s=0x5577f9ada030, vq=0x5577f9b3d2a0) at qemu/hw/block/virtio-blk.c:589 #3 0x00005577f5d4240d in virtio_blk_data_plane_handle_output (vdev=0x5577f9ada030, vq=0x5577f9b3d2a0) at qemu/hw/block/dataplane/virtio-blk.c:158 #4 0x00005577f5d88acd in virtio_queue_notify_aio_vq (vq=0x5577f9b3d2a0) at qemu/hw/virtio/virtio.c:1304 #5 0x00005577f5d8aaaf in virtio_queue_host_notifier_aio_poll (opaque=0x5577f9b3d308) at qemu/hw/virtio/virtio.c:2134 #6 0x00005577f60ca077 in run_poll_handlers_once (ctx=0x5577f79ddbb0) at qemu/aio-posix.c:493 #7 0x00005577f60ca268 in try_poll_mode (ctx=0x5577f79ddbb0, blocking=true) at qemu/aio-posix.c:569 #8 0x00005577f60ca331 in aio_poll (ctx=0x5577f79ddbb0, blocking=true) at qemu/aio-posix.c:601 #9 0x00005577f612722a in bdrv_flush (bs=0x5577f7c20970) at qemu/block/io.c:2403 #10 0x00005577f60c1b2d in bdrv_close (bs=0x5577f7c20970) at qemu/block.c:2322 #11 0x00005577f60c20e7 in bdrv_delete (bs=0x5577f7c20970) at qemu/block.c:2465 #12 0x00005577f60c3ecf in bdrv_unref (bs=0x5577f7c20970) at qemu/block.c:3425 #13 0x00005577f60bf951 in bdrv_root_unref_child (child=0x5577f7a2de70) at qemu/block.c:1361 #14 0x00005577f6112162 in blk_remove_bs (blk=0x5577f7b8ba20) at qemu/block/block-backend.c:491 #15 0x00005577f6111b1b in blk_remove_all_bs () at qemu/block/block-backend.c:245 #16 0x00005577f60c1db6 in bdrv_close_all () at qemu/block.c:2382 #17 0x00005577f5e60cca in main (argc=20, argv=0x7ffea6eb8398, envp=0x7ffea6eb8440) at qemu/vl.c:4684 The key thing is that bdrv_close() uses bdrv_drained_begin() and virtio_queue_host_notifier_aio_poll() must not be called. Thanks to Fam Zheng <famz@redhat.com> for identifying the root cause of this crash. Reported-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Tested-by: Alberto Garcia <berto@igalia.com> Message-id: 20170124095350.16679-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-26s390x/flic: fix compilation of kvm flicCornelia Huck1-1/+1
2c21ee7 ("migration: extend VMStateInfo") missed a void -> int return conversion for kvm_flic_save(). Fixes: 2c21ee7 ("migration: extend VMStateInfo") Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-01-26test-hbitmap: Add hbitmap_is_serializable() callsMax Reitz1-0/+11
Add calls to hbitmap_is_serializable() (asserting that it returns true) where necessary (i.e. before every series of (de-)serialization function invocations). Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20161115225746.3590-3-mreitz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2017-01-26hbitmap: Add hbitmap_is_serializable()Max Reitz2-3/+32
Bitmaps with a granularity of 58 or above can be neither serialized nor deserialized (see the comment in the function added in this series for an explanation). This patch adds a function so that we can check whether a bitmap actually can be (de-)serialized at all, thus avoiding failing the necessary assertion in hbitmap_serialization_granularity(). Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20161115225746.3590-2-mreitz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2017-01-259pfs: fix offset error in v9fs_xattr_read()Greg Kurz1-3/+3
The current code tries to copy `read_count' bytes starting at offset `offset' from a `read_count`-sized iovec. This causes v9fs_pack() to fail with ENOBUFS. Since the PDU iovec is already partially filled with `offset' bytes, let's skip them when creating `qiov_full' and have v9fs_pack() to copy the whole of it. Moreover, this is consistent with the other places where v9fs_init_qiov_from_pdu() is called. This fixes commit "bcb8998fac16 9pfs: call v9fs_init_qiov_from_pdu before v9fs_pack". Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2017-01-259pfs: local: trivial cosmetic fix in pwritev opGreg Kurz1-2/+1
Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-259pfs: fix off-by-one error in PDU free listGreg Kurz1-1/+1
The server can handle MAX_REQ - 1 PDUs at a time and the virtio-9p device has a MAX_REQ sized virtqueue. If the client manages to fill up the virtqueue, pdu_alloc() will fail and the request won't be processed without any notice to the client (it actually causes the linux 9p client to hang). This has been there since the beginning (commit 9f10751365b2 "virtio-9p: Add a virtio 9p device to qemu"), but it needs an agressive workload to run in the guest to show up. We actually allocate MAX_REQ PDUs and I see no reason not to link them all into the free list, so let's fix the init loop. Reported-by: Tuomas Tynkkynen <tuomas@tuxera.com> Suggested-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-25tests: virtio-9p: improve error reportingGreg Kurz1-5/+19
Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-259pfs: add missing coroutine_fn annotationsGreg Kurz1-2/+2
Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-24nios2: Add support for Nios-II R1Marek Vasut7-0/+26
Add remaining bits of the Altera NiosII R1 support into qemu, which is documentation, MAINTAINERS file entry, configure bits, arch_init and configuration files for both linux-user (userland binaries) and softmmu (hardware emulation). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-8-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24nios2: Add Altera 10M50 GHRD emulationMarek Vasut5-0/+431
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the 10M50 development kit with the Nios2 GHRD loaded in the FPGA. It is possible to boot Linux kernel and run userspace, thus far only from initrd as storage support is not yet implemented. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-7-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24nios2: Add periodic timer emulationChris Wulff2-0/+238
Add the Altera timer model. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-6-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24nios2: Add IIC interrupt controller emulationChris Wulff2-0/+104
Add the Altera Nios2 internal interrupt controller model. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-5-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24nios2: Add usermode binaries emulationMarek Vasut11-7/+1148
Add missing bits for qemu-user required for emulating Altera Nios2 userspace binaries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-4-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24nios2: Add disas entriesMarek Vasut3-0/+3541
Add nios2 disassembler support. This patch is composed from binutils files from commit "Opcodes and assembler support for Nios II R2". The files from binutils used in this patch are: include/opcode/nios2.h include/opcode/nios2r1.h include/opcode/nios2r2.h opcodes/nios2-opc.c opcodes/nios2-dis.c Checkpatch says total: 114 errors, 0 warnings, 3609 lines checked , which is caused by a different coding style in those files. These warnings and errors are not addressed To let these files be easily synchronized between binutils and qemu. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-2-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24nios2: Add architecture emulation supportChris Wulff10-0/+2239
Add support for emulating Altera NiosII R1 architecture into qemu. This patch is based on previous work by Chris Wulff from 2012 and updated to latest mainline QEMU. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Cc: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-3-marex@denx.de> [rth: Remove tlb_flush from nios2_cpu_reset.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-24hw/isa/isa-bus: Set category of the "isabus-bridge" deviceThomas Huth1-0/+1
It has "bridge" in its name, so it should be in the category DEVICE_CATEGORY_BRIDGE. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24usb: Set category and description of the MTP deviceThomas Huth1-0/+2
It's a storage device, so let's classify it accordingly. And while we're at it, also add a short description for people who do not know what MTP means. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24gdbstub.c: update old error report statementsZiyue Yang1-5/+5
Some updates from fprintf(stderr, ...) to error_report. Signed-off-by: Ziyue Yang <skiver.cloud.yzy@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24gdbstub.c: fix GDB connection segfault caused by empty machinesZiyue Yang1-0/+7
This patch is to fix the segmentation fault caused by attaching GDB to a QEMU instance initialized with "-M none" option. The bug can be reproduced by > ./qemu-system-x86_64 -M none -nographic -S -s and attach a GDB to it by > gdb -ex 'target remote :1234 The segmentation fault was originally caused by trying to read the information about CPU when communicating with GDB. However, it's impossible for any control flow to exist on an empty machine, nor can CPU's be hot plugged to an empty machine later by QOM commands. So I think simply disabling GDB connections on empty machines makes sense. Signed-off-by: Ziyue Yang <skiver.cloud.yzy@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24scsi-disk: add 'fall through' comment to switch VERIFY casesPeter Maydell1-0/+1
Commit 166dbda7e131 added some extra cases to a switch() such that the existing code is intended to fall through the new case statements. It's clear from the commit that this is intentional, but less clear to subsequent readers of the code, and not clear at all to static analysis tools like Coverity. Add a /* fall through */ comment to indicate the intent. (Fixes CID 1368287.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24Drop duplicate display option documentationSamuel Thibault1-1/+1
The curses and none possibilities are already documented on a separate line, so documenting it on the sdl line was both unneeded and confusing. Introduced in commit f04ec5afbb7d60a56863add800fd90ceee66f362 Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24hw/display/framebuffer.c: Avoid overflow for framebuffers > 4GBPeter Maydell1-1/+1
Coverity points out that calculating src_len by multiplying src_width by rows could overflow. This can only happen in the implausible case of a framebuffer larger than 4GB, but we may as well fix it, placating Coverity. (CID1005515) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24win32: use glib gpoll if glib >= 2.50Marc-André Lureau2-1/+3
A fix has been committed in upstream glib commit 210a9796f78eb90f76f1bd6a304e9fea05e97617. (See also related bug https://bugzilla.gnome.org/show_bug.cgi?id=764415) It is desirable to use the glib version instead of qemu copy, since it provides more debugging facilities (G_MAIN_POLL_DEBUG etc), and hopefully has a better maintainance. Hopefully, we can drop the qemu copy in a few years. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24util/mmap-alloc: refactor a little bit for readabilityCao jin1-6/+4
1st mmap returns *ptr* which aligns to host page size, | size + align | ------------------------------------------ ptr input param *align* could be 1M, or 2M, or host page size. After QEMU_ALIGN_UP, offset will >= 0 2nd mmap use flag MAP_FIXED, then it return ptr+offset, or else fail. If it success, then we will have something like: | offset | size | -------------------------------------- ptr ptr1 *ptr1* is what we really want to return, it equals ptr+offset. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24util/mmap-alloc: check parameter before usingCao jin1-3/+4
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24vfio: remove a duplicated word in commentsCao jin1-2/+2
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-01-24docs: sync pci-ids.txtGerd Hoffmann1-0/+3
Three commits allocated pci ids in include/hw/pci/pci.h without also updating docs/specs/pci-ids.txt: bf439db pci: Allocate PCIe host bridge PCI ID 40d14be hw/pci: introduce PCI Expander Bridge (PXB) 02b0743 hw/pxb: introduce pxb-pcie expander for PCIe machines This patch updates pci-ids.txt accordingly. Cc: qemu-trivial@nongnu.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>