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2020-06-24scripts/tracetool: Update maintainer email addressPhilippe Mathieu-Daudé18-18/+18
2020-06-22docs: Document the RX targetYoshinori Sato3-0/+38
2020-06-22BootLinuxConsoleTest: Test the RX GDB simulatorPhilippe Mathieu-Daudé2-0/+69
2020-06-22hw/rx: Add RX GDB simulatorYoshinori Sato6-0/+215
2020-06-22hw/rx: Register R5F562N7 and R5F562N8 MCUsPhilippe Mathieu-Daudé2-26/+85
2020-06-22hw/rx: Honor -accel qtestRichard Henderson1-1/+8
2020-06-22hw/rx: RX62N microcontroller (MCU)Yoshinori Sato6-0/+339
2020-06-22hw/char: RX62N serial communication interface (SCI)Yoshinori Sato5-0/+407
2020-06-22hw/timer: RX62N compare match timer (CMT)Yoshinori Sato5-2/+329
2020-06-22hw/timer: RX62N 8-Bit timer (TMR)Yoshinori Sato5-0/+538
2020-06-22hw/intc: RX62N interrupt controller (ICUa)Yoshinori Sato5-0/+483
2020-06-22hw/timer/sh_timer: Remove unused 'qemu/timer.h' includePhilippe Mathieu-Daudé1-1/+0
2020-06-22hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'Philippe Mathieu-Daudé4-9/+26
2020-06-22hw/sh4: Use MemoryRegion typedefPhilippe Mathieu-Daudé1-3/+2
2020-06-22MAINTAINERS: Add an entry for common Renesas peripheralsPhilippe Mathieu-Daudé1-1/+8
2020-06-22MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sectionsPhilippe Mathieu-Daudé1-0/+3
2020-06-21tests/acceptance: record/replay tests with advcal imagesPavel Dovgalyuk1-0/+108
2020-06-21tests/acceptance: add record/replay test for m68kPavel Dovgalyuk1-0/+18
2020-06-21tests/acceptance: add record/replay test for ppc64Pavel Dovgalyuk1-0/+16
2020-06-21tests/acceptance: add record/replay test for armPavel Dovgalyuk1-0/+48
2020-06-21tests/acceptance: add record/replay test for aarch64Pavel Dovgalyuk1-0/+19
2020-06-21tests/acceptance: add kernel record/replay test for x86_64Pavel Dovgalyuk1-0/+18
2020-06-21tests/acceptance: add base class record/replay kernel testsPavel Dovgalyuk2-0/+74
2020-06-21MAINTAINERS: Add an entry to review Avocado based acceptance testsPhilippe Mathieu-Daudé1-0/+8
2020-06-19qht: Fix threshold rate calculationRichard Henderson1-1/+2
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2-0/+5
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2-8/+37
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng3-15/+17
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2-0/+8
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng1-1/+23
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng1-1/+3
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2-2/+60
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng2-11/+22
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng2-11/+9
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng1-0/+11
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng1-6/+1
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-15/+14
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-12/+12
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis1-5/+9
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis2-2/+36
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis2-2/+15
2020-06-19hw/intc: Initial commit of lowRISC Ibex PLICAlistair Francis4-0/+327
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis5-0/+609
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis1-1/+2
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis3-26/+24
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis4-41/+63
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis1-2/+7