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* target/hppa: Decode d for cmpb instructionsRichard Henderson2023-11-062-6/+15
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Decode d for bb instructionsRichard Henderson2023-11-062-6/+4
| | | | | | | Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Decode d for sub instructionsRichard Henderson2023-11-062-17/+17
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Decode d for add instructionsRichard Henderson2023-11-062-18/+19
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Decode d for cmpclr instructionsRichard Henderson2023-11-062-8/+9
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Decode d for unit instructionsRichard Henderson2023-11-062-20/+19
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Decode d for logical instructionsRichard Henderson2023-11-062-12/+13
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Remove TARGET_HPPA64Richard Henderson2023-11-064-29/+7
| | | | | | | | Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Drop attempted gdbstub support for hppa64Richard Henderson2023-11-061-19/+13
| | | | | | | | There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Pass d to do_unit_condRichard Henderson2023-11-061-9/+11
| | | | | | | | Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Pass d to do_sed_condRichard Henderson2023-11-061-11/+13
| | | | | | | | Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Pass d to do_log_condRichard Henderson2023-11-061-10/+38
| | | | | | Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Pass d to do_sub_condRichard Henderson2023-11-061-26/+47
| | | | | | Hoist the resolution of d up one level above do_sub_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Pass d to do_condRichard Henderson2023-11-061-28/+54
| | | | | | Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: sar register allows only 5 bits on 32-bit CPUHelge Deller2023-11-061-2/+2
| | | | | | | | | | The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge Deller <deller@gmx.de>
* target/hppa: Mask inputs in copy_iaoq_entryRichard Henderson2023-11-061-2/+14
| | | | | | Ensure that the destination is always a valid GVA offset. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Use copy_iaoq_entry for link in do_ibranchRichard Henderson2023-11-061-1/+1
| | | | | | | | We need to make sure the link is masked properly along the use_nullify_skip path. The other three settings of a link register already use this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]Richard Henderson2023-11-061-13/+22
| | | | | | | | | | | This will be how we ensure that the IAOQ is always valid per PSW.W, therefore all stores to these two variables must be done with this function. Use third argument -1 if the destination is always dynamic, and fourth argument NULL if the destination is always static. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Pass DisasContext to copy_iaoq_entryRichard Henderson2023-11-061-19/+20
| | | | | | Interface change only, no functional effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix hppa64 addressingRichard Henderson2023-11-062-13/+16
| | | | | | | In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Adjust hppa_cpu_dump_state for hppa64Richard Henderson2023-11-061-9/+19
| | | | | | | Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Handle absolute addresses for pa2.0Richard Henderson2023-11-062-2/+44
| | | | | | | With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Update cpu_hppa_get/put_psw for hppa64Richard Henderson2023-11-061-11/+52
| | | | | | | With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement hppa_cpu_class_by_nameRichard Henderson2023-11-061-1/+9
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement cpu_listRichard Henderson2023-11-062-0/+29
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Make HPPA_BTLB_ENTRIES variableRichard Henderson2023-11-063-27/+35
| | | | | | Depend on hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Introduce TYPE_HPPA64_CPURichard Henderson2023-11-064-15/+26
| | | | | | | | Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix extrw and depw with sar for hppa64Richard Henderson2023-11-061-2/+5
| | | | | | These are 32-bit operations regardless of processor. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix bb_sar for hppa64Richard Henderson2023-11-061-3/+13
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix do_add, do_sub for hppa64Richard Henderson2023-11-061-18/+32
| | | | | | | Select the proper carry bit for input to the arithmetic and for output for the condition. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix trans_ds for hppa64Richard Henderson2023-11-061-11/+37
| | | | | | | This instruction always uses the input carry from bit 32, but produces all 16 output carry bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Truncate rotate count in trans_shrpw_sarRichard Henderson2023-11-061-1/+4
| | | | | | When forcing rotate by i32, the shift count must be as well. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix load in do_load_32Richard Henderson2023-11-061-1/+1
| | | | | | | | The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32 not tcg_gen_qemu_ld_reg. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix hppa64 case in machine.cRichard Henderson2023-11-061-2/+2
| | | | | | Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Remove load_constRichard Henderson2023-11-061-14/+7
| | | | | | | Replace with tcg_constant_reg. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Remove get_temp_tlRichard Henderson2023-11-061-25/+3
| | | | | | | Replace with tcg_temp_new_tl without recording into ctx. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Remove get_tempRichard Henderson2023-11-061-45/+31
| | | | | | | Replace with tcg_temp_new without recording into ctx. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Populate an interval tree with valid tlb entriesRichard Henderson2023-11-064-71/+167
| | | | | | | Complete the data structure conversion started earlier. This reduces the perf overhead of hppa_get_physical_address from ~5% to ~0.25%. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Split out hppa_flush_tlb_rangeRichard Henderson2023-11-061-15/+24
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Always report one page to tlb_set_pageRichard Henderson2023-11-062-4/+12
| | | | | | | No need to trigger the large_page_mask code unnecessarily. Drop the now unused HPPATLBEntry.page_size field. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Use IntervalTreeNode in HPPATLBEntryRichard Henderson2023-11-063-19/+23
| | | | | | | Replace the va_b and va_b fields with the interval tree node. The actual interval tree is not yet used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Rename hppa_tlb_entry to HPPATLBEntryRichard Henderson2023-11-063-22/+22
| | | | | | Rename to CamelCase per coding style. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Include PSW_P in tb flags and mmu indexRichard Henderson2023-11-064-27/+30
| | | | | | | | | Use a separate mmu index for PSW_P enabled vs disabled. This means we can elide the tlb flush in cpu_hppa_put_psw when PSW_P changes. This turns out to be the majority of all tlb flushes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* meson: Rename target_softmmu_arch -> target_system_archPhilippe Mathieu-Daudé2023-10-071-1/+1
| | | | | | | | | | | | | | | | Finish the convertion started with commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"). If the $target_type is 'system', then use the target_system_arch[] source set :) Mechanical change doing: $ sed -i -e s/target_softmmu_arch/target_system_arch/g \ $(git grep -l target_softmmu_arch) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-13-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson2023-10-041-1/+0
| | | | | | | | | This function is now empty, so remove it. In the case of m68k and tricore, this empties the class instance initfn, so remove those as well. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson2023-10-042-3/+3
| | | | | Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-79/+78
| | | | | | | Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson2023-10-031-1/+0
| | | | | | | | Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/*: Add instance_align to all cpu base classesRichard Henderson2023-10-031-0/+1
| | | | | | | | The omission of alignment has technically been wrong since 269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Wire up diag instruction to support BTLBHelge Deller2023-09-193-3/+105
| | | | | | | | | | | | Wire up the hppa diag instruction to support Block-TLBs when called with the 0x100 value. The diag_btlb() helper function does all necessary steps to emulate the PDC BTLB firmware function, which includes providing BTLB info, adding a new BTLB, deleting a BTLB and removing all BTLBs. Signed-off-by: Helge Deller <deller@gmx.de>