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path: root/target/i386/cpu.c (follow)
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* i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAXSean Christopherson2021-09-301-0/+20
* i386: Add primary SGX CPUID and MSR definesSean Christopherson2021-09-301-2/+2
* target/i386: Added VGIF V_IRQ masking capabilityLara Lazier2021-09-131-2/+5
* target/i386: Moved int_ctl into CPUX86State structureLara Lazier2021-09-131-1/+1
* target/i386: Added VGIF featureLara Lazier2021-09-131-1/+2
* target/i386: VMRUN and VMLOAD canonicalizationsLara Lazier2021-09-131-8/+11
* i386/cpu: Remove AVX_VNNI feature from Cooperlake cpu modelYang Zhong2021-08-251-1/+1
* target/i386: Remove split lock detect in Snowridge CPU modelChenyi Qiang2021-08-251-0/+8
* docs: Update path that mentions deprecated.rstMao Zhongyi2021-07-271-1/+1
* i386: do not call cpudef-only models functions for max, host, baseClaudio Fontana2021-07-231-2/+17
* target/i386: Fix cpuid level for AMDzhenwei pi2021-07-131-2/+9
* target/i386: suppress CPUID leaves not defined by the CPU vendorMichael Roth2021-07-131-0/+6
* i386: expand Hyper-V features during CPU feature expansion timeVitaly Kuznetsov2021-07-131-0/+4
* target/i386: Populate x86_ext_save_areas offsets using cpuid where possibleDavid Edmondson2021-07-061-12/+1
* target/i386: Make x86_ext_save_areas visible outside cpu.cDavid Edmondson2021-07-061-6/+1
* target/i386: kvm: add support for TSC scalingPaolo Bonzini2021-06-251-1/+1
* i386: run accel_cpu_instance_init as post_initClaudio Fontana2021-06-041-3/+7
* i386: reorder call to cpu_exec_realizefnClaudio Fontana2021-06-041-28/+51
* i386: drop FEAT_HYPERV feature leavesVitaly Kuznetsov2021-05-311-88/+0
* i386: keep hyperv_vendor string up-to-dateVitaly Kuznetsov2021-05-311-10/+9
* i386: use better matching family/model/stepping for 'max' CPUDaniel P. Berrangé2021-05-311-0/+6
* i386: use better matching family/model/stepping for 'qemu64' CPUDaniel P. Berrangé2021-05-311-3/+3
* target/i386/cpu: Constify X86CPUDefinitionPhilippe Mathieu-Daudé2021-05-311-6/+7
* target/i386/cpu: Constify CPUCachesPhilippe Mathieu-Daudé2021-05-311-4/+4
* target/i386: Add CPU model versions supporting 'xsaves'Vitaly Kuznetsov2021-05-311-56/+94
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into...Peter Maydell2021-05-281-10/+20
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| * cpu: Move CPUClass::get_paging_enabled to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-1/+3
| * cpu: Move CPUClass::get_memory_mapping to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-1/+1
| * cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-1/+1
| * cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-1/+1
| * cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-4/+4
| * cpu: Move CPUClass::get_crash_info to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-1/+1
| * cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-261-1/+1
| * cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-261-0/+8
| * cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-261-1/+1
* | i386/cpu: Expose AVX_VNNI instruction to guestYang Zhong2021-05-261-2/+2
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* i386: split off sysemu part of cpu.cClaudio Fontana2021-05-101-379/+6
* accel: introduce new accessor functionsClaudio Fontana2021-05-101-7/+2
* cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefnClaudio Fontana2021-05-101-13/+7
* i386: split cpu accelerators from cpu.c, using AccelCPUClassClaudio Fontana2021-05-101-342/+41
* i386: Add missing cpu feature bits in EPYC-Rome modelBabu Moger2021-04-091-0/+12
* target/i386: allow modifying TCG phys-addr-bitsPaolo Bonzini2021-03-191-15/+8
* Various spelling fixesMichael Tokarev2021-03-091-1/+1
* target/i386: Add bus lock debug exception supportChenyi Qiang2021-02-251-1/+1
* target/i386: update to show preferred boolean syntax for -cpuDaniel P. Berrangé2021-02-251-1/+1
* i386: Add the support for AMD EPYC 3rd generation processorsBabu Moger2021-02-181-1/+106
* sev/i386: Add initial support for SEV-ESTom Lendacky2021-02-161-0/+1
* target/i386: Expose VMX entry/exit load pkrs control bitsChenyi Qiang2021-02-081-2/+2
* target/i86: implement PKSPaolo Bonzini2021-02-081-2/+2
* x86/cpu: Populate SVM CPUID feature bitsWei Huang2021-02-081-3/+3