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* target/tricore: Fix helper_ret() not correctly restoring PSWBastian Koppelmann2023-06-211-4/+4
| | | | | | | | | | | | | We are always taking the TRICORE_FEATURE_13 branch as every CPU has TRICORE_FEATURE_13. For CPUs with ISA > 1.3 we have to take the else branch. We fix this by inverting the condition. We check for TRICORE_FEATURE_131, which every CPU except TRICORE_FEATURE_13 CPUs have. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1700 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-5-kbastian@mail.uni-paderborn.de>
* target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regsBastian Koppelmann2023-06-211-2/+9
| | | | | | | | | | some insns were not checking if an even index was used to access a 64 bit register. In the worst case that could lead to a buffer overflow as reported in https://gitlab.com/qemu-project/qemu/-/issues/1698. Reported-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-4-kbastian@mail.uni-paderborn.de>
* target/tricore: Correctly fix saving PSW.CDE to CSA on callBastian Koppelmann2023-06-211-1/+6
| | | | | | | | we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-3-kbastian@mail.uni-paderborn.de>
* target/tricore: Fix out-of-bounds index in imask instructionSiqi Chen2023-06-211-0/+1
| | | | | | | | | | | | When translating "imask" instruction of Tricore architecture, QEMU did not check whether the register index was out of bounds, resulting in a global-buffer-overflow. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698 Reported-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612065633.149152-1-coc.cyqh@gmail.com> Message-Id: <20230612113245.56667-2-kbastian@mail.uni-paderborn.de>
* target/tricore: Add DISABLE insn variantBastian Koppelmann2023-06-212-1/+11
| | | | | | | | | | this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext as with the other DISABLE insn. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-9-kbastian@mail.uni-paderborn.de>
* target/tricore: Implement SYCSCALL insnBastian Koppelmann2023-06-211-1/+1
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-8-kbastian@mail.uni-paderborn.de>
* target/tricore: Add shuffle insnBastian Koppelmann2023-06-214-0/+46
| | | | | | | | | | | this is based on code by volumit (https://github.com/volumit/qemu/). Reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 and https://gitlab.com/qemu-project/qemu/-/issues/1452. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-7-kbastian@mail.uni-paderborn.de>
* target/tricore: Add crc32.b insnBastian Koppelmann2023-06-214-0/+17
| | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-6-kbastian@mail.uni-paderborn.de>
* target/tricore: Add crc32l.w insnBastian Koppelmann2023-06-214-5/+23
| | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-5-kbastian@mail.uni-paderborn.de>
* target/tricore: Add LHA insnBastian Koppelmann2023-06-212-3/+20
| | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-4-kbastian@mail.uni-paderborn.de>
* target/tricore: Add popcnt.w insnBastian Koppelmann2023-06-212-0/+8
| | | | | | | | reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-3-kbastian@mail.uni-paderborn.de>
* target/tricore: Introduce ISA 1.6.2 featureBastian Koppelmann2023-06-212-0/+14
| | | | | | | | we also introduce the tc37x CPU that implements that ISA version. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-2-kbastian@mail.uni-paderborn.de>
* meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé2023-06-201-2/+2
| | | | | | | | | | | | | | | | We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Remove pointless CONFIG_SOFTMMU guardPhilippe Mathieu-Daudé2023-06-201-2/+0
| | | | | | | | | | | | We don't build any user emulation target for Tricore, only the system emulation. No need to check for it as it is always defined. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230613133347.82210-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Fix wrong PSW for call insnsBastian Koppelmann2023-06-071-0/+2
| | | | | | | | | | we were copying PSW into a local variable, updated PSW.CDE in the local and never wrote it back. So when we called save_context_upper() we were using the non-local version of PSW which did not contain the updated PSW.CDE. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230526061946.54514-6-kbastian@mail.uni-paderborn.de>
* target/tricore: Refactor PCXI/ICR register fieldsBastian Koppelmann2023-06-074-56/+123
| | | | | | | | | | starting from ISA version 1.6.1 (previously known as 1.6P/E), some bitfields in PCXI and ICR have changed. We also refactor these registers using the register fields API. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1453 Message-Id: <20230526061946.54514-5-kbastian@mail.uni-paderborn.de>
* accel/tcg: Introduce translator_io_startRichard Henderson2023-06-051-2/+0
| | | | | | | | | New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson2023-06-051-0/+5
| | | | | | | | | | | | | | In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/*: Add missing includes of tcg/debug-assert.hRichard Henderson2023-06-051-0/+1
| | | | | | | | This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Use min/max for saturateRichard Henderson2023-03-131-11/+3
| | | | | | | Use tcg_constant_i32 for the bounds. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Avoid tcg_const_i32Richard Henderson2023-03-131-63/+64
| | | | | | | All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Drop some temp initializationRichard Henderson2023-03-131-2/+2
| | | | | | | | The temp variables here are always set afterward; the initialization with a constant was discarded. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Use setcondi instead of explicit allocationRichard Henderson2023-03-131-5/+2
| | | | | | | This removes the only use of temp. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Rename t_off10 and use tcg_constant_i32Richard Henderson2023-03-131-29/+27
| | | | | | | | While temp3 could simply be initialized with tcg_constant_i32, the renaming makes the purpose clearer. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Split t_n as constant from temp as variableRichard Henderson2023-03-131-128/+140
| | | | | | | As required, allocate temp separately. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Remove `NB_MMU_MODES` defineAnton Johansson2023-03-131-1/+0
| | | | | | | | | Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230306175230.7110-22-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* gdbstub: move register helpers into standalone includeAlex Bennée2023-03-071-1/+1
| | | | | | | | | | | | | | | | | These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
* target/tricore: Drop tcg_temp_freeRichard Henderson2023-03-051-536/+4
| | | | | | | Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson2023-03-011-1/+1
| | | | | | | | In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Replace `tb_pc()` with `tb->pc`Anton Johansson2023-03-011-1/+2
| | | | | | | Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230227135202.9710-14-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Remove unused fields from CPUTriCoreStatePhilippe Mathieu-Daudé2023-02-271-11/+0
| | | | | | | | | | | | | | Remove dead code: - unused fields in CPUTriCoreState - (unexisting) tricore_def_t structure - forward declaration of tricore_boot_info structure (declared in "hw/tricore/tricore.h", used once in hw/tricore/tricore_testboard.c). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230117184217.83305-1-philmd@linaro.org>
* target/tricore: Fix OPC1_16_SRO_LD_H translationAnton Kochkov2023-02-081-1/+1
| | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Eitan Eliahu <eitan_eliahu@hotmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652 Message-Id: <20230112142258.514079-1-anton.kochkov@proton.me> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target/tricore: Fix OPC2_32_BO_LD_BU_PREINCBastian Koppelmann2023-02-081-1/+1
| | | | | | | | | | we were sign extending the result of the load, while the instruction clearly states that the result should be unsigned. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-10-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target/tricore: Fix OPC2_32_RRRR_DEXTRBastian Koppelmann2023-02-081-3/+12
| | | | | | | | | | | | | if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the right by 32 which is undefined behaviour. In this case the TriCore would do nothing an just return the higher register cpu_reg_d[r1]. We fixed that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower register. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-8-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target/tricore: Fix RRPW_DEXTRBastian Koppelmann2023-02-081-9/+3
| | | | | | | | | | | | | if we used const16 == 0 we would crash qemu with the error: ../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed This whole instruction can be handled by 'tcg_gen_extract2_tl' which takes care of this special case as well. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-6-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target/tricore: Fix OPC2_32_RCRW_INSERT translationBastian Koppelmann2023-02-081-2/+2
| | | | | | | | | | | | we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target/tricore: Fix OPC2_32_RCRW_IMASK translationBastian Koppelmann2023-02-081-3/+3
| | | | | | | | | | | | we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé2023-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'hwaddr' type is defined in "exec/hwaddr.h" as: hwaddr is the type of a physical address (its size can be different from 'target_ulong'). All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: $ fgrep define include/exec/hwaddr.h #define HWADDR_H #define HWADDR_BITS 64 #define HWADDR_MAX UINT64_MAX #define TARGET_FMT_plx "%016" PRIx64 ^^^^^^ #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 #define HWADDR_PRIu PRIu64 #define HWADDR_PRIx PRIx64 #define HWADDR_PRIX PRIX64 Since hwaddr's size can be *different* from target_ulong, it is very confusing to read one of its format using the 'TARGET_FMT_' prefix, normally used for the target_long / target_ulong types: $ fgrep TARGET_FMT_ include/exec/cpu-defs.h #define TARGET_FMT_lx "%08x" #define TARGET_FMT_ld "%d" #define TARGET_FMT_lu "%u" #define TARGET_FMT_lx "%016" PRIx64 #define TARGET_FMT_ld "%" PRId64 #define TARGET_FMT_lu "%" PRIu64 Apparently this format was missed during commit a8170e5e97 ("Rename target_phys_addr_t to hwaddr"), so complete it by doing a bulk-rename with: $ sed -i -e s/TARGET_FMT_plx/HWADDR_FMT_plx/g $(git grep -l TARGET_FMT_plx) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230110212947.34557-1-philmd@linaro.org> [thuth: Fix some warnings from checkpatch.pl along the way] Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/tricore: Fix gdbstub write to address registersRichard Henderson2022-12-181-1/+1
| | | | | | | | Typo had double-writes to data registers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1363 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Convert to 3-phase resetPeter Maydell2022-12-162-5/+9
| | | | | | | | | | | | | | | | Convert the tricore CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20221124115023.2437291-19-peter.maydell@linaro.org
* target/tricore: Rename csfr.def -> csfr.h.incPhilippe Mathieu-Daudé2022-11-052-2/+2
| | | | | | | | | | | | | | | We use the .h.inc extension to include C headers. To be consistent with the rest of the codebase, rename the C headers using the .def extension. IDE/tools using our .editorconfig / .gitattributes will leverage this consistency. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221025235006.7215-4-philmd@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* accel/tcg: Remove will_exit argument from cpu_restore_stateRichard Henderson2022-11-011-1/+1
| | | | | | | | | The value passed is always true, and if the target's synchronize_from_tb hook is non-trivial, not exiting may be erroneous. Reviewed-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/tricore: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-262-6/+11
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-041-1/+1
| | | | | | | | | | | The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/core: Add CPUClass.get_pcRichard Henderson2022-10-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core) Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core) Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core) Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core) Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs) Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs) Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs) Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs) Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs) Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs) Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs) Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+4
| | | | | | | | | | | Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Normalize header guard symbol definitionMarkus Armbruster2022-05-111-1/+1
| | | | | | | | | | | We commonly define the header guard symbol without an explicit value. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-4-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-3/+3
| | | | | | | | | | | | | G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+4
| | | | | | | | | | We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0
| | | | | | Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>