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| * target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASKRichard Henderson2024-02-031-7/+0
| | | | | | | | | | | | | | | | | | These macros are no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-23-richard.henderson@linaro.org>
| * target/sparc: Split fcc out of env->fsrRichard Henderson2024-02-034-522/+198
| | | | | | | | | | | | | | | | | | | | Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>
| * target/sparc: Remove cpu_fsrRichard Henderson2024-02-033-113/+114
| | | | | | | | | | | | | | | | | | | | | | Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>
| * target/sparc: Split cexc and ftt from env->fsrRichard Henderson2024-02-034-38/+48
| | | | | | | | | | | | | | | | | | | | These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>
| * target/sparc: Merge check_ieee_exceptions with FPop helpersRichard Henderson2024-02-033-129/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an exception is to be raised, the destination fp register should be unmodified. The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[]. We can simplify the entire implementation by having each FPOp helper call check_ieee_exceptions. For the moment this requires that all FPop helpers write to the TCG global cpu_fsr, so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org>
| * target/sparc: Clear cexc and ftt in do_check_ieee_exceptionsRichard Henderson2024-02-032-16/+2
| | | | | | | | | | | | | | | | | | | | Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org>
| * target/sparc: Split ver from env->fsrRichard Henderson2024-02-033-16/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This field is read-only. It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org>
| * target/sparc: Introduce cpu_get_fsr, cpu_put_fsrRichard Henderson2024-02-037-12/+70
| | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>
| * target/sparc: Remove qt0, qt1 temporariesRichard Henderson2024-02-033-8/+0
| | | | | | | | | | | | | | | | | | These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FdmulqRichard Henderson2024-02-033-16/+9
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FdTOq, FxTOqRichard Henderson2024-02-033-10/+11
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FsTOq, FiTOqRichard Henderson2024-02-033-10/+11
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FCMPq, FCMPEqRichard Henderson2024-02-033-52/+41
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FqTOd, FqTOxRichard Henderson2024-02-033-9/+10
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FqTOs, FqTOiRichard Henderson2024-02-033-9/+10
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVqRichard Henderson2024-02-033-28/+26
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org>
| * target/sparc: Use i128 for FSQRTqRichard Henderson2024-02-033-8/+32
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>
| * target/sparc: Inline FNEG, FABSRichard Henderson2024-02-033-72/+30
| | | | | | | | | | | | | | | | | | | | | | | | These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>
| * target/sparc: Introduce gen_{load,store}_fpr_QRichard Henderson2024-02-031-6/+19
| | | | | | | | | | | | | | | | | | | | Use them for trans_FMOVq. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-5-richard.henderson@linaro.org>
| * target/sparc: Remove gen_dest_fpr_FRichard Henderson2024-02-031-11/+6
| | | | | | | | | | | | | | | | | | | | Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-4-richard.henderson@linaro.org>
| * target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILLRichard Henderson2024-02-031-16/+15
| | | | | | | | | | | | | | | | | | | | Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org>
| * target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPYRichard Henderson2024-02-031-19/+26
| | | | | | | | | | | | | | | | | | | | Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-2-richard.henderson@linaro.org>
| * include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson2024-02-0318-22/+21
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * include/exec: Implement cpu_mmu_index genericallyRichard Henderson2024-02-0329-133/+8
| | | | | | | | | | | | | | | | For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/xtensa: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/tricore: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/sparc: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-28/+35
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/sh4: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-10/+22
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/s390x: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/s390x: Split out s390x_env_mmu_indexRichard Henderson2024-02-032-17/+21
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/rx: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/riscv: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | | | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/riscv: Replace cpu_mmu_index with riscv_env_mmu_indexRichard Henderson2024-02-033-8/+9
| | | | | | | | | | | | | | | | | | Use the target-specific function name in preference to the generic name. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_indexRichard Henderson2024-02-032-3/+3
| | | | | | | | | | | | | | | | | | Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/ppc: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/ppc: Split out ppc_env_mmu_indexRichard Henderson2024-02-034-9/+14
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/openrisc: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-8/+15
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/nios2: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-6/+13
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/mips: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/mips: Split out mips_env_mmu_indexRichard Henderson2024-02-036-10/+15
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fillRichard Henderson2024-02-032-20/+16
| | | | | | | | | | | | | | | | | | | | | | Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/microblaze: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-12/+19
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/m68k: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/loongarch: Rename MMU_IDX_*Richard Henderson2024-02-035-9/+9
| | | | | | | | | | | | | | | | The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/loongarch: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-4/+13
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/i386: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-7/+16
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/hppa: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-5/+14
| | | | | | | | | | | | Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/cris: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/cris: Cache mem_index in DisasContextRichard Henderson2024-02-032-13/+7
| | | | | | | | | | | | | | Compute this value once for each translation. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/avr: Populate CPUClass.mmu_indexRichard Henderson2024-02-032-3/+7
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>