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| * | target/i386: do not use s->tmp4 for pushPaolo Bonzini2023-12-291-1/+1
| | | | | | | | | | | | | | | | | | | | | Just create a temporary for the occasion. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: split eflags computation out of gen_compute_eflagsPaolo Bonzini2023-12-291-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new x86 decoder wants the gen_* functions to compute EFLAGS before writeback, which can be an issue for instructions with a memory destination such as ARPL or shifts. Extract code to compute the EFLAGS without clobbering CC_SRC, in case the memory write causes a fault. The flags writeback mechanism will take care of copying the result to CC_SRC. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: do not clobber T0 on string operationsPaolo Bonzini2023-12-291-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | The new decoder would rather have the operand in T0 when expanding SCAS, rather than use R_EAX directly as gen_scas currently does. This makes SCAS more similar to CMP and SUB, in that CC_DST = T0 - T1. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: do not clobber A0 in POP translationPaolo Bonzini2023-12-291-14/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new decoder likes to compute the address in A0 very early, so the gen_lea_v_seg in gen_pop_T0 would clobber the address of the memory operand. Instead use T0 since it is already available and will be overwritten immediately after. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: do not decode string source/destination into decode->memPaolo Bonzini2023-12-291-18/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | decode->mem is only used if one operand has has_ea == true. String operations will not use decode->mem and will load A0 on their own, because they are the only case of two memory operands in a single instruction. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: add X86_SPECIALs for MOVSX and MOVZXPaolo Bonzini2023-12-293-24/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usually the registers are just moved into s->T0 without much care for their operand size. However, in some cases we can get more efficient code if the operand fetching logic syncs with the emission function on what is nicer. All the current uses are mostly demonstrative and only reduce the code in the emission functions, because the instructions do not support memory operands. However the logic is generic and applies to several more instructions such as MOVSXD (aka movslq), one-byte shift instructions, multiplications, XLAT, and indirect calls/jumps. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: rename zext0/zext2 and make them closer to the manualPaolo Bonzini2023-12-292-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86_SPECIAL_ZExtOp0 and X86_SPECIAL_ZExtOp2 are poorly named; they are a hack that is needed by scalar insertion and extraction instructions, and not really related to zero extension: for PEXTR the zero extension is done by the generation functions, for PINSR the high bits are not used at all and in fact are *not* filled with zeroes when loaded into s->T1. Rename the values to match the effect described in the manual, and explain better in the comments. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: avoid trunc and ext for MULX and RORXPaolo Bonzini2023-12-291-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use _tl operations for 32-bit operands on 32-bit targets, and only go through trunc and extu ops for 64-bit targets. While the trunc/ext ops should be pretty much free after optimization, the optimizer also does not like having the same temporary used in multiple EBBs. Therefore it is nicer to not use tmpN* unless necessary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: reimplement check for validity of LOCK prefixPaolo Bonzini2023-12-293-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | The previous check erroneously allowed CMP to be modified with LOCK. Instead, tag explicitly the instructions that do support LOCK. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: document more deviations from the manualPaolo Bonzini2023-12-291-0/+12
| | | | | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: clean up cpu_cc_compute_allPaolo Bonzini2023-12-296-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_cc_compute_all() has an argument that is always equal to CC_OP for historical reasons (dating back to commit a7812ae4123, "TCG variable type checking.", 2008-11-17, which added the argument to helper_cc_compute_all). It does not make sense for the argument to have any other value, so remove it and clean up some lines that are not too long anymore. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: remove unnecessary truncationsPaolo Bonzini2023-12-292-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | gen_lea_v_seg (called by gen_add_A0_ds_seg) already zeroes any bits of s->A0 beyond s->aflag. It does so before summing the segment base and, if not in 64-bit mode, also after summing it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: remove unnecessary arguments from raise_interruptPaolo Bonzini2023-12-293-7/+5
| | | | | | | | | | | | | | | | | | | | | is_int is always 1, and error_code is always zero. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: speedup JO/SETO after MUL or IMULPaolo Bonzini2023-12-291-0/+3
| | | | | | | | | | | | | | | | | | | | | OF is equal to the carry flag, so use the same CCPrepare. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | target/i386: optimize computation of JL and JLE from flagsPaolo Bonzini2023-12-291-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take advantage of the fact that there can be no 1 bits between SF and OF. If they were adjacent, you could sum SF and get a carry only if SF was already set. Then the value of OF in the sum is the XOR of OF itself, the carry (which is SF) and 0 (the value of the OF bit in the addend): this is OF^SF exactly. Because OF and SF are not adjacent, just place more 1 bits to the left so that the carry propagates, which means summing CC_O - CC_S. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | | target/sparc: Constify VMState in machine.cRichard Henderson2023-12-291-4/+4
| | | | | | | | | | | | | | | | | | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-18-richard.henderson@linaro.org>
* | | target/s390x: Constify VMState in machine.cRichard Henderson2023-12-291-16/+16
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-17-richard.henderson@linaro.org>
* | | target/riscv: Constify VMState in machine.cRichard Henderson2023-12-291-14/+14
| | | | | | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-16-richard.henderson@linaro.org>
* | | target/ppc: Constify VMState in machine.cRichard Henderson2023-12-291-16/+16
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-15-richard.henderson@linaro.org>
* | | target/openrisc: Constify VMState in machine.cRichard Henderson2023-12-291-4/+4
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-14-richard.henderson@linaro.org>
* | | target/mips: Constify VMState in machine.cRichard Henderson2023-12-291-13/+13
| | | | | | | | | | | | | | | | | | | | | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-13-richard.henderson@linaro.org>
* | | target/microblaze: Constify VMState in machine.cRichard Henderson2023-12-291-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-12-richard.henderson@linaro.org>
* | | target/m68k: Constify VMState in machine.cRichard Henderson2023-12-291-8/+8
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-11-richard.henderson@linaro.org>
* | | target/loongarch: Constify VMState in machine.cRichard Henderson2023-12-291-9/+9
| | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231221031652.119827-10-richard.henderson@linaro.org>
* | | target/i386: Constify VMState in machine.cRichard Henderson2023-12-291-64/+64
| | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231221031652.119827-9-richard.henderson@linaro.org>
* | | target/hppa: Constify VMState in machine.cRichard Henderson2023-12-291-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-8-richard.henderson@linaro.org>
* | | target/cris: Constify VMState in machine.cRichard Henderson2023-12-291-3/+3
| | | | | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-7-richard.henderson@linaro.org>
* | | target/avr: Constify VMState in machine.cRichard Henderson2023-12-291-1/+1
| | | | | | | | | | | | | | | | | | | | | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-6-richard.henderson@linaro.org>
* | | target/alpha: Constify VMState in machine.cRichard Henderson2023-12-291-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-5-richard.henderson@linaro.org>
* | | target/arm: Constify hvf/hvf.cRichard Henderson2023-12-291-5/+8
| | | | | | | | | | | | | | | | | | | | | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-4-richard.henderson@linaro.org>
* | | target/arm: Constify VMState in machine.cRichard Henderson2023-12-291-27/+27
| |/ |/| | | | | | | | | | | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-3-richard.henderson@linaro.org>
* | target/riscv/kvm: do not use non-portable strerrorname_np()Natanael Copa2023-12-231-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | strerrorname_np is non-portable and breaks building with musl libc. Use strerror(errno) instead, like we do other places. Cc: qemu-stable@nongnu.org Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error msg) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2041 Buglink: https://gitlab.alpinelinux.org/alpine/aports/-/issues/15541 Signed-off-by: Natanael Copa <ncopa@alpinelinux.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | target/loongarch: Add timer information dump supportBibo Mao2023-12-211-0/+2
|/ | | | | | | | | | | Timer emulation sometimes is problematic especially when vm is running in kvm mode. This patch adds registers dump support relative with timer hardware, so that it is easier to find the problems. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231206081839.2290178-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* Merge tag 'pull-request-2023-12-20' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2023-12-202-1/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Add compat machines for QEMU 9.0 * Some header clean-ups by Philippe * Restrict type names to alphanumerical range (and a few special characters) * Fix analyze-migration.py script on s390x * Clean up and improve some tests * Document handling of commas in CLI options parameters # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmWCtYsRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWLnw//cNJrxG0V+j0iakX+C7HRumVrLBDI4KYY # Cp2Hx92SyeQ0Kk8DJS6JueTV0SLjMsV77APu2YPH7ELmPlk+CB9gqmV7xVoYNvsm # QbRPlIjFw8MHLekadc2A+C+pn48tWACoOdBEDIfazKrxybnf0B57RC/fIfMKHjbs # 2ALCoFbbgphs7yWuzTHK8ayKaGMhUVkWfzHQwpnq899olHyZBhkl951uKJA6VmLx # KvggePkpszLjmmXA8MH1hDCcizki31cB0ZKTbQFCyE42s2S3Hvg0GueU90O7Y1cj # lS5tPVQxyEhUYMLL+/hudlf2OYqVn2BalB7ieUQIy6rG8yoc9zxfIKQi0ccl+2oA # s8HRq5S0bSjtilQogU1LQL/Gk6W1/N9MmnhKvCGB+BTK5KX7s4EQk02y9gGZm/8s # pMErMyaXTG4dLiTAK42VgMVDqCYvzBmE+Gj91OmoUR7fb+VMrsWxeBFxMPDn+VtL # TMJegIFsjw2QCSitcU4v+nP0qtKgXGbuZtrGXKabrxH5PmeQFJDSM7TwpTK4qvjK # QMIQKBbz8BfJnUzN8qAaaJEpp1T5tcMJClKtfcgxq/+VyaSaHLmD0cljqBC+g+y7 # FTo+fa7oYx44sAlqapdEXBSGn4T+J26iuCef13CCCiPfYBv/tk3b2E0AWHj4y58I # +VpInjUaPBQ= # =TA1/ # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Dec 2023 04:36:11 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-12-20' of https://gitlab.com/thuth/qemu: tests/unit/test-qmp-event: Replace fixture by global variables tests/unit/test-qmp-event: Simplify event emission check tests/unit/test-qmp-event: Drop superfluous mutex tests/qtest/npcm7xx_pwm-test: Only do full testing in slow mode qemu-options: Clarify handling of commas in options parameters tests/qtest/migration-test: Fix analyze-migration.py for s390x qom/object: Limit type names to alphanumerical and some few special characters tests/unit/test-io-task: Rename "qemu:dummy" to avoid colon in the name memory: Remove "qemu:" prefix from the "qemu:ram-discard-manager" type name hw: Replace anti-social QOM type names (again) docs/system/arm: Fix for rename of type "xlnx.bbram-ctrl" target: Restrict 'sysemu/reset.h' to system emulation hw/s390x/ipl: Remove unused 'exec/exec-all.h' included header hw/misc/mips_itu: Remove unnecessary 'exec/exec-all.h' header hw/ppc/spapr_hcall: Remove unused 'exec/exec-all.h' included header system/qtest: Restrict QTest API to system emulation system/qtest: Include missing 'hw/core/cpu.h' header MAINTAINERS: Add some more vmware-related files to the corresponding section hw: Add compat machines for 9.0 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target: Restrict 'sysemu/reset.h' to system emulationPhilippe Mathieu-Daudé2023-12-202-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | vCPU "reset" is only possible with system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-ID: <20231212113640.30287-5-philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | target/arm/helper: Propagate MDCR_EL2.HPMN into PMCR_EL0.NJean-Philippe Brucker2023-12-191-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MDCR_EL2.HPMN allows an hypervisor to limit the number of PMU counters available to EL1 and EL0 (to keep the others to itself). QEMU already implements this split correctly, except for PMCR_EL0.N reads: the number of counters read by EL1 or EL0 should be the one configured in MDCR_EL2.HPMN. Cc: qemu-stable@nongnu.org Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20231215144652.4193815-2-jean-philippe@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/tcg: Including missing 'exec/exec-all.h' headerPhilippe Mathieu-Daudé2023-12-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | translate_insn() ends up calling probe_access_full(), itself declared in "exec/exec-all.h": TranslatorOps::translate_insn -> aarch64_tr_translate_insn() -> is_guarded_page() -> probe_access_full() Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231130142519.28417-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accelPhilippe Mathieu-Daudé2023-12-191-0/+5
| | | | | | | | | | | | | | | | | | Hardware accelerators handle that in *hardware*. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231130142519.28417-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm: Restrict TCG specific helpersPhilippe Mathieu-Daudé2023-12-192-55/+55
| | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231130142519.28417-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 onlyPeter Maydell2023-12-192-22/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditionally. This was OK when all our CPUs supported AArch32 EL1, but we have quite a lot of CPU models now which only support AArch64 at EL1: a64fx cortex-a76 cortex-a710 neoverse-n1 neoverse-n2 neoverse-v1 Only define these registers for CPUs which allow AArch32 EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231121144605.3980419-1-peter.maydell@linaro.org
* | target/arm/kvm: Have kvm_arm_hw_debug_active take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-17-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_handle_debug take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-16-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_handle_dabt_nisv take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-191-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-15-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_verify_ext_dabt_pending take a ARMCPU argPhilippe Mathieu-Daudé2023-12-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-14-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_[get|put]_virtual_time take ARMCPU argumentPhilippe Mathieu-Daudé2023-12-191-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-13-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_vcpu_finalize take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_vcpu_init take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-191-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_pmu_set_irq take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-192-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_pmu_init take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-192-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/arm/kvm: Have kvm_arm_pvtime_init take a ARMCPU argumentPhilippe Mathieu-Daudé2023-12-192-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>