summary refs log tree commit diff stats
path: root/target (follow)
Commit message (Collapse)AuthorAgeFilesLines
* meson: make target endianneess available to KconfigPaolo Bonzini2024-05-031-0/+3
| | | | | | | | | | Some targets use "default y" for boards to filter out those that require TCG. For consistency we are switching all other targets to do the same. MIPS boards may only be available for big-endian or only for little-endian emulators, add a symbol so that this can be described with a "depends on" clause. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386: switch boards to "default y"Paolo Bonzini2024-05-031-0/+1
| | | | | | | | | | | Some targets use "default y" for boards to filter out those that require TCG. For consistency we are switching all other targets to do the same. Continue with i386. No changes to generated config-devices.mak files, other than adding CONFIG_I386 to the x86_64-softmmu target. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: ppc: disable sPAPR code if CONFIG_PSERIES is disabledPaolo Bonzini2024-05-031-4/+13
| | | | | | | | | | target/ppc/kvm.c calls out to code in hw/ppc/spapr*.c; that code is not present and fails to link if CONFIG_PSERIES is not enabled. Adjust kvm.c to depend on CONFIG_PSERIES instead of TARGET_PPC64, and compile out anything that requires cap_papr, because only the pseries machine will call kvmppc_set_papr(). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Kconfig: kvm: allow building without any boardPaolo Bonzini2024-05-032-0/+4
| | | | | | | | | | | | | | | KVM code might have to call functions on the PCIDevice that is passed to kvm_arch_fixup_msi_route(). This fails in the case where --without-default-devices is used and no board is configured. While this is not really a useful configuration, and therefore setting up stubs for CONFIG_PCI is overkill, failing the build is impolite. Just include the PCI subsystem if kvm_arch_fixup_msi_route() requires it, as is the case for ARM and x86. Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: Give IRQs a chance when resetting HF_INHIBIT_IRQ_MASKRuihan Li2024-05-031-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When emulated with QEMU, interrupts will never come in the following loop. However, if the NOP instruction is uncommented, interrupts will fire as normal. loop: cli call do_sti jmp loop do_sti: sti # nop ret This behavior is different from that of a real processor. For example, if KVM is enabled, interrupts will always fire regardless of whether the NOP instruction is commented or not. Also, the Intel Software Developer Manual states that after the STI instruction is executed, the interrupt inhibit should end as soon as the next instruction (e.g., the RET instruction if the NOP instruction is commented) is executed. This problem is caused because the previous code may choose not to end the TB even if the HF_INHIBIT_IRQ_MASK has just been reset (e.g., in the case where the STI instruction is immediately followed by the RET instruction), so that IRQs may not have a change to trigger. This commit fixes the problem by always terminating the current TB to give IRQs a chance to trigger when HF_INHIBIT_IRQ_MASK is reset. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ruihan Li <lrh2000@pku.edu.cn> Message-ID: <20240415064518.4951-4-lrh2000@pku.edu.cn> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge tag 'pull-target-arm-20240430' of ↵Richard Henderson2024-04-3010-34/+126
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/core/clock: allow clock_propagate on child clocks * hvf: arm: Remove unused PL1_WRITE_MASK define * target/arm: Restrict translation disabled alignment check to VMSA * docs/system/arm/emulation.rst: Add missing implemented features * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max' * tests/avocado: update sunxi kernel from armbian to 6.6.16 * target/arm: Make new CPUs default to 1GHz generic timer * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian * hw/arm: Add DM163 display to B-L475E-IOT01A board # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYxILcZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pRzD/40UZrhNbS+FEANkXJ7qpUm # giCKn8hVwteWY4T4LugUK9987lU0HZ7CGfsHoSaWNwa7RBdKUoDRqi/CQ1kCfeDO # XET42do+6SJhak+4wmzEfYD+K7wnlauun0/dyqCjd2+JP0bln/MIY5r8JCN1GiYS # YSAAKoZqAfG1bC3HmxELI9min09GPT+tzw0PAyVJipRtfE+ykZXoCytu0GWU5jB+ # VBI6SGmqMPd/c/7JfJV8KP8R0Mn3etA3hbOCx7YDL6cUmbepWtNPV8dLeTwofrpa # 01uqN83PpbbSYr96QdXXa7Ov105hQH7e8jmr9+7jTpd3f9U7+GwsxxqDR1KDHLgn # pUGZneoTDTkJugfXM28A0VoVB3eyJYPCLE9QQ/HXpChXc62NOQV5jcECgLiUDujH # hVbeGEG0KViQlhMUfI3vIfTaIjEALDcNw5bxVUCqg8vdO6UtTXqqWdaS4Xgne8HB # KeCu5xXngXEZjIgidZkmIC15FD60B19JdQz2WR+6BDCw8Ajm9iPWlj+ftZztuX/S # cFSUZ05BPbTkBzAHG4GBvjXTdwsxX2acGBNtdETOQAxhkoRcug0Pn+BmrZQLqkm5 # mPKPW9FFxIkkgeK/ZdA4uIEwDZX/LQlnrX129XGt7DVr+yDNKekaVGfLL8x8alT1 # 3v0Ni/nntc6QtZDB88OIzA== # =vAf/ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Apr 2024 09:47:51 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240430' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits) tests/qtest : Add testcase for DM163 hw/arm : Connect DM163 to B-L475E-IOT01A hw/arm : Create Bl475eMachineState hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC hw/display : Add device DM163 hw/arm/npcm7xx: Store derivative OTP fuse key in little endian hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields target/arm: Default to 1GHz cntfrq for 'max' and new CPUs hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz target/arm: Refactor default generic timer frequency handling tests/avocado: update sunxi kernel from armbian to 6.6.16 target/arm: Enable FEAT_Spec_FPACC for -cpu max target/arm: Implement ID_AA64MMFR3_EL1 target/arm: Enable FEAT_ETS2 for -cpu max target/arm: Enable FEAT_CSV2_3 for -cpu max docs/system/arm/emulation.rst: Add missing implemented features target/arm: Restrict translation disabled alignment check to VMSA hvf: arm: Remove PL1_WRITE_MASK ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Default to 1GHz cntfrq for 'max' and new CPUsPeter Maydell2024-04-306-8/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In previous versions of the Arm architecture, the frequency of the generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. In Armv8.6, the architecture standardized this frequency to 1GHz. Because there is no ID register feature field that indicates whether a CPU is v8.6 or that it ought to have this counter frequency, we implement this by changing our default CNTFRQ value for all CPUs, with exceptions for backwards compatibility: * CPU types which we already implement will retain the old default value. None of these are v8.6 CPUs, so this is architecturally OK. * CPUs used in versioned machine types with a version of 9.0 or earlier will retain the old default value. The upshot is that the only CPU type that changes is 'max'; but any new type we add in future (whether v8.6 or not) will also get the new 1GHz default. It remains the case that the machine model can override the default value via the 'cntfrq' QOM property (regardless of the CPU type). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
| * target/arm: Refactor default generic timer frequency handlingPeter Maydell2024-04-303-25/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer frequency is settable by board code via a QOM property "cntfrq", but otherwise defaults to 62.5MHz. The way this is done includes some complication resulting from how this was originally a fixed value with no QOM property. Clean it up: * always set cpu->gt_cntfrq_hz to some sensible value, whether the CPU has the generic timer or not, and whether it's system or user-only emulation * this means we can always use gt_cntfrq_hz, and never need the old GTIMER_SCALE define * set the default value in exactly one place, in the realize fn The aim here is to pave the way for handling the ARMv8.6 requirement that the generic timer frequency is always 1GHz. We're going to do that by having old CPU types keep their legacy-in-QEMU behaviour and having the default for any new CPU types be a 1GHz rather han 62.5MHz cntfrq, so we want the point where the default is decided to be in one place, and in code, not in a DEFINE_PROP_UINT64() initializer. This commit should have no behavioural changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
| * target/arm: Enable FEAT_Spec_FPACC for -cpu maxPeter Maydell2024-04-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_Spec_FPACC is a feature describing speculative behaviour in the event of a PAC authontication failure when FEAT_FPACCOMBINE is implemented. FEAT_Spec_FPACC means that the speculative use of pointers processed by a PAC Authentication is not materially different in terms of the impact on cached microarchitectural state (caches, TLBs, etc) between passing and failing of the PAC Authentication. QEMU doesn't do speculative execution, so we can advertise this feature. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
| * target/arm: Implement ID_AA64MMFR3_EL1Peter Maydell2024-04-304-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | Newer versions of the Arm ARM (e.g. rev K.a) now define fields for ID_AA64MMFR3_EL1. Implement this register, so that we can set the fields if we need to. There's no behaviour change here since we don't currently set the register value to non-zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
| * target/arm: Enable FEAT_ETS2 for -cpu maxPeter Maydell2024-04-302-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_ETS2 is a tighter set of guarantees about memory ordering involving translation table walks than the old FEAT_ETS; FEAT_ETS has been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1 now gives no greater guarantees than ETS == 0. FEAT_ETS2 requires: * the virtual address of a load or store that appears in program order after a DSB cannot be translated until after the DSB completes (section B2.10.9) * TLB maintenance operations that only affect translations without execute permission are guaranteed complete after a DSB (R_BLDZX) * if a memory access RW2 is ordered-before memory access RW2, then RW1 is also ordered-before any translation table walk generated by RW2 that generates a Translation, Address size or Access flag fault (R_NNFPF, I_CLGHP) As with FEAT_ETS, QEMU is already compliant, because we do not reorder translation table walk memory accesses relative to other memory accesses, and we always guarantee to have finished TLB maintenance as soon as the TLB op is done. Update the documentation to list FEAT_ETS2 instead of the no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
| * target/arm: Enable FEAT_CSV2_3 for -cpu maxPeter Maydell2024-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose information about whether branch targets and branch history trained in one hardware described context can control speculative execution in a different hardware context. There is no branch prediction in TCG, so we don't need to do anything to be compliant with this. Upadte the '-cpu max' ID registers to advertise the feature. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
| * target/arm: Restrict translation disabled alignment check to VMSARichard Henderson2024-04-301-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For cpus using PMSA, when the MPU is disabled, the default memory type is Normal, Non-cachable. This means that it should not have alignment restrictions enforced. Cc: qemu-stable@nongnu.org Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") Reported-by: Clément Chigot <chigot@adacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Clément Chigot <chigot@adacore.com> Message-id: 20240422170722.117409-1-richard.henderson@linaro.org [PMM: trivial comment, commit message tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hvf: arm: Remove PL1_WRITE_MASKZenghui Yu2024-04-301-1/+0
| | | | | | | | | | | | | | | | | | | | As it had never been used since the first commit a1477da3ddeb ("hvf: Add Apple Silicon support"). Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge tag 'pull-request-2024-04-30' of https://gitlab.com/thuth/qemu into ↵Richard Henderson2024-04-304-34/+28
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Clean-ups for "errp" handling in s390x cpu_model code * Fix a possible abort in the "edu" device * Add missing qga stubs for stand-alone qga builds and re-enable qga-ssh-test * Fix memory corruption caused by the stm32l4x5 uart device * Update the s390x custom runner to Ubuntu 22.04 * Fix READ NATIVE MAX ADDRESS IDE commands to avoid a possible crash * Shorten the runtime of Cirrus-CI jobs # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmYwmaMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUCERAAss5PJMG8rI4i4X/3nW49JYTlPOpgm/YX # /UWF+eHUlqaqDdE0s+Pdw4Ozo3hXQt/E/CkcyflUTzVpnZtpv9vkhNWyjOoPV31v # GQyQEzGvxZXl2S595XefyAyaMTP5maBhUTlyZWJo385cQraa60Ot5d4Mibr2CobY # gIBRxEGB/frJYpbHJPxd/FxJV120gtuWAdZwGGYYYjwMzf2IKu2veODB8CnUErlX # WNUsIzjtAslfh8Ek2ZmPzD7uktCUeigkukqIrLC1oEU3wzbJHkISv1kXCKPW/Nf6 # ISjVa5TqGwkiiF8fw9aYKvWrnPJS7JkhXw7Gz+b39d846kUdNyDfgLcYJeNS3cZ2 # R1xgR9B6hX8ZmikMbGC+0/Sv15u2Yr+bFxJBTJzq6zdOAb9EJNQY1hW2w/Lbrg3X # LjY+ltcVweoSILT6AE6vGDPCHfBzO+6FcptFvw7ePvRGOlwAPZ3tEB9G2LEbCYgg # BjWNP4aRuSfbUebO4x4Todz65WN8aY1EIBXORU/wgUlF2+zajWiOI5JRDKjWz2qQ # gAMeCbLplli5bYrChWtouRIXtb061cQloULddu/SRFcaJOlV3SCzx4JfN15pU90s # jRMIhMESAEj4NSfclhxsOiYp3ywZTvlQsVA6MgPlu2i3HJakQnt5zbg59TesRn2d # r5PfAk83UnA= # =0OB7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Apr 2024 12:11:31 AM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] * tag 'pull-request-2024-04-30' of https://gitlab.com/thuth/qemu: .gitlab-ci.d/cirrus: Remove the netbsd and openbsd jobs .gitlab-ci.d/cirrus.yml: Shorten the runtime of the macOS and FreeBSD jobs tests/qtest/ide-test: Verify READ NATIVE MAX ADDRESS is not limited hw/ide/core.c (cmd_read_native_max): Avoid limited device parameters gitlab: remove stale s390x-all-linux-static conf hacks gitlab: migrate the s390x custom machine to 22.04 build-environment: make some packages optional hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size qga: Re-enable the qga-ssh-test when running without fuzzing stubs: Add missing qga stubs hw: misc: edu: use qemu_log_mask instead of hw_error hw: misc: edu: rename local vars in edu_check_range hw: misc: edu: fix 2 off-by-one errors target/s390x/cpu_models_sysemu: Drop local @err in apply_cpu_model() target/s390x/cpu_models: Make kvm_s390_apply_cpu_model() return boolean target/s390x/cpu_models: Drop local @err in get_max_cpu_model() target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return boolean target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model() target/s390x/cpu_model: Make check_compatibility() return boolean Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/s390x/cpu_models_sysemu: Drop local @err in apply_cpu_model()Zhao Liu2024-04-301-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use @errp to fetch error information directly and drop the local variable @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-8-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | target/s390x/cpu_models: Make kvm_s390_apply_cpu_model() return booleanZhao Liu2024-04-303-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As error.h suggested, the best practice for callee is to return something to indicate success / failure. So make kvm_s390_apply_cpu_model() return boolean and check the returned boolean in apply_cpu_model() instead of accessing @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-7-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | target/s390x/cpu_models: Drop local @err in get_max_cpu_model()Zhao Liu2024-04-301-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use @errp to fetch error information directly and drop the local variable @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-6-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return booleanZhao Liu2024-04-303-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As error.h suggested, the best practice for callee is to return something to indicate success / failure. So make kvm_s390_get_host_cpu_model() return boolean and check the returned boolean in get_max_cpu_model() instead of accessing @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-5-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model()Zhao Liu2024-04-301-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use @errp to fetch error information directly and drop the local variable @err. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-3-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * | target/s390x/cpu_model: Make check_compatibility() return booleanZhao Liu2024-04-301-7/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | As error.h suggested, the best practice for callee is to return something to indicate success / failure. With returned boolean, there's no need to check @err. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-2-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Merge tag 'pull-loongarch-20240429' of https://gitlab.com/gaosong/qemu into ↵Richard Henderson2024-04-301-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Add boot LoongArch elf kernel with FDT v2: Fix 'make check-tcg' fail. # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZi8F3AAKCRBAov/yOSY+ # 35VrBADb6f1mYNUTG5iDvKppvA8RG1TybxfXfgA+Z9vPkJqFkT6wt8J+JFwgh3UT # w0xY2Y2xZkPjxnUpEhZiVJjp5hk+BEzr3vE4M5DzKC1vpCYpbojxxN6FB41Up862 # kS7slW6XsZgKpLLvUkFttPt3G4DUN29CscVgy4Ci0zrqyNjnsw== # =ufbc # -----END PGP SIGNATURE----- # gpg: Signature made Sun 28 Apr 2024 07:28:44 PM PDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240429' of https://gitlab.com/gaosong/qemu: hw/loongarch: Add cells missing from rtc node hw/loongarch: Add cells missing from uart node hw/loongarch: fdt remove unused irqchip node hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: Init efi_fdt table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_system_table hw/loongarch: Add init_cmdline hw/loongarch: Add slave cpu boot_code hw/loongarch: Add load initrd hw/loongarch: Move boot functions to boot.c Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/loongarch: Add init_cmdlineSong Gao2024-04-291-0/+2
| |/ | | | | | | | | | | | | | | Add init_cmline and set boot_info->a0, a1 Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240426091551.2397867-5-gaosong@loongson.cn>
* | target/riscv/kvm: remove sneaky strerrorname_np() instanceDaniel Henrique Barboza2024-04-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d424db2354 excluded some strerrorname_np() instances because they break musl libc builds. Another instance happened to slip by via commit d4ff3da8f4. Remove it before it causes trouble again. Fixes: d4ff3da8f4 (target/riscv/kvm: initialize 'vlenb' via get-reg-list) Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | target/loongarch/cpu.c: typo fix: expectionMichael Tokarev2024-04-291-1/+1
| | | | | | | | | | | | Fixes: 1590154ee437 ("target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'") Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* | target/ppc/cpu_init: Remove "PowerPC" prefix from the CPU listThomas Huth2024-04-291-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Printing a "PowerPC" in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cpu" parameter, too, and it also takes some precious space in the dense output of the CPU entries. Let's simply remove this now and use two spaces at the beginning of the lines for the indentation of the entries instead, and add a "Available CPUs" in the very first line, like most other target architectures are doing it for their CPU help output already. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | target/s390x/cpu_models: Rework the output of "-cpu help"Thomas Huth2024-04-291-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Printing an "s390x" in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cpu" parameter, too, and it also takes some precious space in the dense output of the CPU entries. Let's simply remove this now! While we're at it, use two spaces at the beginning of the lines for the indentation of the entries, and add a "Available CPUs" in the very first line, like most other target architectures are doing it for their "-cpu help" output already. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | target/i386/cpu: Remove "x86" prefix from the CPU listThomas Huth2024-04-291-1/+1
|/ | | | | | | | | | | | | | | | Printing an "x86" in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cpu" parameter, too, and it also takes some precious space in the dense output of the CPU entries. Let's simply remove this now and use two spaces at the beginning of the lines for the indentation of the entries instead, like most other target architectures are doing it for their CPU help output already. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' headerPhilippe Mathieu-Daudé2024-04-263-0/+4
| | | | | | | | | | | | | The CPUBreakpoint and CPUWatchpoint structures are declared in "hw/core/cpu.h", which contains declarations related to CPUState and CPUClass. Some source files only require the BP/WP definitions and don't need to pull in all CPU* API. In order to simplify, create a new "exec/breakpoint.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240418192525.97451-3-philmd@linaro.org>
* accel/hvf: Use accel-specific per-vcpu @dirty fieldPhilippe Mathieu-Daudé2024-04-263-5/+5
| | | | | | | | | | | HVF has a specific use of the CPUState::vcpu_dirty field (CPUState::vcpu_dirty is not used by common code). To make this field accel-specific, add and use a new @dirty variable in the AccelCPUState structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424174506.326-4-philmd@linaro.org>
* accel/nvmm: Use accel-specific per-vcpu @dirty fieldPhilippe Mathieu-Daudé2024-04-261-10/+11
| | | | | | | | | | | NVMM has a specific use of the CPUState::vcpu_dirty field (CPUState::vcpu_dirty is not used by common code). To make this field accel-specific, add and use a new @dirty variable in the AccelCPUState structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424174506.326-3-philmd@linaro.org>
* accel/whpx: Use accel-specific per-vcpu @dirty fieldPhilippe Mathieu-Daudé2024-04-261-11/+12
| | | | | | | | | | | WHPX has a specific use of the CPUState::vcpu_dirty field (CPUState::vcpu_dirty is not used by common code). To make this field accel-specific, add and use a new @dirty variable in the AccelCPUState structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424174506.326-2-philmd@linaro.org>
* target/i386: Include missing 'exec/exec-all.h' headerPhilippe Mathieu-Daudé2024-04-261-0/+1
| | | | | | | | | The XRSTOR instruction ends calling tlb_flush(), declared in "exec/exec-all.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231211212003.21686-13-philmd@linaro.org>
* target/sparc: Replace abi_ulong by uint32_t for TARGET_ABI32Philippe Mathieu-Daudé2024-04-261-1/+1
| | | | | | | | | | We have abi_ulong == uint32_t for the 32-bit ABI. Use the generic type to avoid to depend on the "exec/user/abitypes.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240418192525.97451-14-philmd@linaro.org>
* target/ppc/excp_helper: Avoid 'abi_ptr' in system emulationPhilippe Mathieu-Daudé2024-04-261-1/+1
| | | | | | | | | | | | 'abi_ptr' is a user specific type. The system emulation equivalent is 'target_ulong'. Use it in ppc_ldl_code() to emphasis this is not an user emulation function. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231211212003.21686-18-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'Philippe Mathieu-Daudé2024-04-2628-61/+65
| | | | | | | | | | | | | | | | | | | accel/tcg/ files requires the following definitions: - TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20231211212003.21686-4-philmd@linaro.org>
* gdbstub: Avoid including 'cpu.h' in 'gdbstub/helpers.h'Philippe Mathieu-Daudé2024-04-262-0/+2
| | | | | | | | | We only need the "exec/tswap.h" and "cpu-param.h" headers. Only include "cpu.h" in the target gdbstub.c source files. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240418192525.97451-20-philmd@linaro.org>
* accel: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2024-04-263-0/+3
| | | | | | | | | Theses files call cpu_ldl_code() which is declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231211212003.21686-5-philmd@linaro.org>
* exec: Expose 'target_page.h' API to user emulationPhilippe Mathieu-Daudé2024-04-262-12/+0
| | | | | | | | | | User-only objects might benefit from the "exec/target_page.h" API, which allows to build some objects once for all targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231211212003.21686-3-philmd@linaro.org>
* exec: Rename NEED_CPU_H -> COMPILING_PER_TARGETPhilippe Mathieu-Daudé2024-04-261-2/+2
| | | | | | | | | | | | | | | | | | 'NEED_CPU_H' guard target-specific code; it is defined by meson altogether with the 'CONFIG_TARGET' definition. Rename NEED_CPU_H as COMPILING_PER_TARGET to clarify its meaning. Mechanical change running: $ sed -i s/NEED_CPU_H/COMPILING_PER_TARGET/g $(git grep -l NEED_CPU_H) then manually add a /* COMPILING_PER_TARGET */ comment after the '#endif' when the block is large. Inspired-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240322161439.6448-4-philmd@linaro.org>
* Merge tag 'hw-misc-20240425' of https://github.com/philmd/qemu into stagingRichard Henderson2024-04-254-102/+113
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc HW patch queue - Script to compare machines compat_props[] (Maksim) - Introduce 'module' CPU topology level (Zhao) - Various cleanups (Thomas, Zhao, Inès, Bernhard) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYqN3wACgkQ4+MsLN6t # wN4hTw/9FHsItnEkme/864DRPSP7A9mCGa+JfzJmsL8oUb9fBjXXKm+lNchMLu3B # uvzfXB2Ea24yf5vyrldo0XlU3i/4GDvqXTI6YFYqBvitGICauYBu+6n2NZh2Y/Pn # zZCcVo167o0q7dHu2WSrZ6cSUchsF2C80HjuS07QaN2YZ7QMuN1+uqTjCQ/JHQWA # MH4xHh7cXdfCbbv8iNhMWn6sa+Bw/UyfRcc2W6w9cF5Q5cuuTshgDyd0JBOzkM1i # Mcul7TuKrSiLUeeeqfTjwtw3rtbNfkelV3ycgvgECFAlzPSjF5a6d/EGdO2zo3T/ # aFZnQBYrb4U0SzsmfXFHW7cSylIc1Jn2CCuZZBIvdVcu8TGDD5XsgZbGoCfKdWxp # l67qbQJy1Mp3LrRzygJIaxDOfE8fhhRrcIxfK/GoTHaCkqeFRkGjTeiDTVBqAES2 # zs6kUYZyG/xGaa2tsMu+HbtSO5EEqPC2QCdHayY3deW42Kwjj/HFV50Ya8YgYSVp # gEAjTDOle2dDjlkYud+ymTJz7LnGb3G7q0EZRI9DWolx/bu+uZGQqTSRRre4qFQY # SgN576hsFGN4NdM7tyJWiiqD/OC9ZeqUx3gGBtmI52Q6obBCE9hcow0fPs55Tk95 # 1YzPrt/3IoPI5ZptCoA8DFiysQ46OLtpIsQO9YcrpJmxWyLDSr0= # =tm+U # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 03:59:08 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'hw-misc-20240425' of https://github.com/philmd/qemu: (22 commits) hw/core: Support module-id in numa configuration hw/core: Introduce module-id as the topology subindex hw/core/machine: Support modules in -smp hw/core/machine: Introduce the module as a CPU topology level hw/i386/pc_sysfw: Remove unused parameter from pc_isa_bios_init() hw/misc : Correct 5 spaces indents in stm32l4x5_exti hw/xtensa: Include missing 'exec/cpu-common.h' in 'bootparam.h' hw/elf_ops: Rename elf_ops.h -> elf_ops.h.inc hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device hw: Fix problem with the A*MPCORE switches in the Kconfig files hw/riscv/virt: Replace sprintf by g_strdup_printf hw/misc/imx: Replace sprintf() by snprintf() hw/misc/applesmc: Simplify DeviceReset handler target/i386: Move APIC related code to cpu-apic.c hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h scripts: add script to compare compatibility properties python/qemu/machine: add method to retrieve QEMUMachine::binary field ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/i386: Move APIC related code to cpu-apic.cPhilippe Mathieu-Daudé2024-04-254-102/+113
| | | | | | | | | | | | | | | | | | | | Move APIC related code split in cpu-sysemu.c and monitor.c to cpu-apic.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240321154838.95771-4-philmd@linaro.org>
* | Merge tag 'pull-target-arm-20240425' of ↵Richard Henderson2024-04-2527-53/+341
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement FEAT_NMI and NMI support in the GICv3 * hw/dma: avoid apparent overflow in soc_dma_set_request * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code * Add ResetType argument to Resettable hold and exit phase methods * Add RESET_TYPE_SNAPSHOT_LOAD ResetType * Implement STM32L4x5 USART # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYqMhMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3uVlD/47U3zYP33y4+wJcRScC0QI # jYd82jS7GhD5YP5QPrIEMaSbDwtYGi4Rez1taaHvZ2fWLg2gE973iixmTaM2mXCd # xPEqMsRXkFrQnC89K5/v9uR04AvHxoM8J2mD2OKnUT0RVBs38WxCUMLETBsD18/q # obs1RzDRhEs5BnwwPMm5HI1iQeVvDRe/39O3w3rZfA8DuqerrNOQWuJd43asHYjO # Gc1QzCGhALlXDoqk11IzjhJ7es8WbJ5XGvrSNe9QLGNJwNsu9oi1Ez+5WK2Eht9r # eRvGNFjH4kQY1YCShZjhWpdzU9KT0+80KLirMJFcI3vUztrYZ027/rMyKLHVOybw # YAqgEUELwoGVzacpaJg73f77uknKoXrfTH25DfoLX0yFCB35JHOPcjU4Uq1z1pfV # I80ZcJBDJ95mXPfyKLrO+0IyVBztLybufedK2aiH16waEGDpgsJv66FB2QRuQBYW # O0i6/4DEUZmfSpOmr8ct+julz7wCWSjbvo6JFWxzzxvD0M5T3AFKXZI244g1SMdh # LS8V7WVCVzVJ5mK8Ujp2fVaIIxiBzlXVZrQftWv5rhyDOiIIeP8pdekmPlI6p5HK # 3/2efzSYNL2UCDZToIq24El/3md/7vHR6DBfBT1/pagxWUstqqLgkJO42jQtTG0E # JY1cZ/EQY7cqXGrww8lhWA== # =WEsU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 03:36:03 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits) tests/qtest: Add tests for the STM32L4x5 USART hw/arm: Add the USART to the stm32l4x5 SoC hw/char/stm32l4x5_usart: Add options for serial parameters setting hw/char/stm32l4x5_usart: Enable serial read and write hw/char: Implement STM32L4x5 USART skeleton reset: Add RESET_TYPE_SNAPSHOT_LOAD docs/devel/reset: Update to new API for hold and exit phase methods hw, target: Add ResetType argument to hold and exit phase methods scripts/coccinelle: New script to add ResetType to hold and exit phases allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code hw/dma: avoid apparent overflow in soc_dma_set_request hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI target/arm: Add FEAT_NMI to max hw/intc/arm_gicv3: Report the VINMI interrupt hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() hw/intc/arm_gicv3: Implement NMI interrupt priority hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() hw/intc/arm_gicv3: Add NMI handling CPU interface registers ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell2024-04-2517-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. Pass the type to all three of the phase methods to avoid having to do that. Commit created with for dir in hw target include; do \ spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/reset-type.cocci \ --keep-comments --smpl-spacing --in-place \ --include-headers --dir $dir; done and no manual edits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
| * | target/arm: Add FEAT_NMI to maxJinjie Ruan2024-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable FEAT_NMI on the 'max' CPU. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()Jinjie Ruan2024-04-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority) come from the hcrx_el2.HCRX_VFNMI bit. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Handle PSTATE.ALLINT on taking an exceptionJinjie Ruan2024-04-251-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set or clear PSTATE.ALLINT on taking an exception to ELx according to the SCTLR_ELx.SPINTMASK bit. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMIJinjie Ruan2024-04-252-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Add support for NMI in arm_phys_excp_target_el()Jinjie Ruan2024-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in arm_phys_excp_target_el(). Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Add support for Non-maskable InterruptJinjie Ruan2024-04-255-16/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>