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* tcg/i386: Use TEST r,r to test 8/16/32 bitsPaolo Bonzini2024-02-031-0/+17
| | | | | | | | | | Just like when testing against the sign bits, TEST r,r can be used when the immediate is 0xff, 0xff00, 0xffff, 0xffffffff. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Improve TSTNE/TESTEQ vs powers of twoRichard Henderson2024-02-033-8/+53
| | | | | | | Use "test x,x" when the bit is one of the 4 sign bits. Use "bt imm,x" otherwise. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Support TCG_COND_TST{EQ,NE}Richard Henderson2024-02-032-37/+60
| | | | | | | Merge tcg_out_testi into tcg_out_cmp and adjust the two uses. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmpRichard Henderson2024-02-031-11/+13
| | | | | | | Return the x86 condition codes to use after the compare. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Pass x86 condition codes to tcg_out_cmovRichard Henderson2024-02-031-8/+8
| | | | | | | Hoist the tcg_cond_to_jcc index outside the function. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson2024-02-031-1/+2
| | | | | | | | Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson2024-02-031-0/+2
| | | | | | | Define as 0 for all tcg backends. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediatesPaolo Bonzini2024-01-111-0/+11
| | | | | | | | | | | In the case where OR or XOR has an 8-bit immediate between 128 and 255, we can operate on a low-byte register and shorten the output by two or three bytes (two if a prefix byte is needed for REX.B). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231228120524.70239-1-pbonzini@redhat.com> [rth: Incorporate into switch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: convert add/sub of 128 to sub/add of -128Paolo Bonzini2024-01-111-15/+34
| | | | | | | | | | | Extend the existing conditional that generates INC/DEC, to also swap an ADD for a SUB and vice versa when the immediate is 128. This facilitates using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231228120514.70205-1-pbonzini@redhat.com> [rth: Use a switch on C] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson2023-11-061-2/+0
| | | | | | | The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson2023-11-061-2/+0
| | | | | | | The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
* tcg/i386: Use tcg_use_softmmuRichard Henderson2023-10-221-101/+99
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé2023-10-071-1/+1
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-6-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Add tcg_out_tb_start backend hookRichard Henderson2023-09-161-0/+5
| | | | | | | | This hook may emit code at the beginning of the TB. Suggested-by: Jordan Niethe <jniethe5@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: pass vece to tcg_target_const_match()Jiajie Chen2023-09-151-1/+1
| | | | | | | | | | | Pass vece to tcg_target_const_match() to allow correct interpretation of const args of vector ops. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230908022302.180442-4-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Implement negsetcond_*Richard Henderson2023-08-242-10/+26
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use shift in tcg_out_setcondRichard Henderson2023-08-241-0/+15
| | | | | | | For LT/GE vs zero, shift down the sign bit. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Clear dest first in tcg_out_setcond if possibleRichard Henderson2023-08-241-1/+16
| | | | | | | | Using XOR first is both smaller and more efficient, though cannot be applied if it clobbers an input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use CMP+SBB in tcg_out_setcondRichard Henderson2023-08-241-0/+50
| | | | | | | Use the carry bit to optimize some forms of setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Merge tcg_out_movcond{32,64}Richard Henderson2023-08-241-21/+7
| | | | | | | | Pass a rexw parameter instead of duplicating the functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Merge tcg_out_setcond{32,64}Richard Henderson2023-08-241-17/+7
| | | | | | | | Pass a rexw parameter instead of duplicating the functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Merge tcg_out_brcond{32,64}Richard Henderson2023-08-241-61/+49
| | | | | | | | Pass a rexw parameter instead of duplicating the functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce negsetcond opcodesRichard Henderson2023-08-241-0/+2
| | | | | | | Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson2023-08-241-2/+1
| | | | | | | | | | | Replace the separate defines with TCG_TARGET_HAS_extr_i64_i32, so that the two parts of backend-specific type changing cannot be out of sync. Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: <20230822175127.1173698-1-richard.henderson@linaro.org>
* tcg/i386: Allow immediate as input to deposit_*Richard Henderson2023-08-242-5/+23
| | | | | | | | We can use MOVB and MOVW with an immediate just as easily as with a register input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Drop BYTEH deposits for 64-bitRichard Henderson2023-08-244-8/+6
| | | | | | | | It is more useful to allow low-part deposits into all registers than to restrict allocation for high-byte deposits. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Output %gs prefix in tcg_out_vex_opcRichard Henderson2023-08-121-0/+3
| | | | | | | | | Missing the segment prefix means that user-only fails to add guest_base for some 128-bit load/store. Fixes: 098d0fc10d2 ("tcg/i386: Support 128-bit load/store") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1763 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/{i386, s390x}: Add earlyclobber to the op_add2's first outputIlya Leoshkevich2023-07-232-2/+5
| | | | | | | | | | | | | | | | | | | | | | | i386 and s390x implementations of op_add2 require an earlyclobber, which is currently missing. This breaks VCKSM in s390x guests. E.g., on x86_64 the following op: add2_i32 tmp2,tmp3,tmp2,tmp3,tmp3,tmp2 dead: 0 2 3 4 5 pref=none,0xffff is translated to: addl %ebx, %r12d adcl %r12d, %ebx Introduce a new C_N1_O1_I4 constraint, and make sure that earlyclobber of aliased outputs is honored. Cc: qemu-stable@nongnu.org Fixes: 82790a870992 ("tcg: Add markup for output requires new register") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230719221310.1968845-7-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Split out tcg-target-reg-bits.hRichard Henderson2023-06-052-2/+16
| | | | | | | | Often, the only thing we need to know about the TCG host is the register size. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add tlb_fast_offset to TCGContextRichard Henderson2023-06-051-4/+5
| | | | | | | | Disconnect the layout of ArchCPU from TCG compilation. Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITSRichard Henderson2023-05-301-1/+0
| | | | | | | | The last use was removed by e77c89fb086a. Fixes: e77c89fb086a ("cputlb: Remove static tlb sizing") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Support 128-bit load/storeRichard Henderson2023-05-302-5/+190
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use host/cpuinfo.hRichard Henderson2023-05-232-129/+22
| | | | | | | | | | | | | Use the CPUINFO_* bits instead of the individual boolean variables that we had been using. Remove all of the init code that was moved over to cpuinfo-i386.c. Note that have_avx512* check both AVX512{F,VL}, as we had previously done during tcg_target_init. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add tlb_dyn_max_bits to TCGContextRichard Henderson2023-05-161-1/+1
| | | | | | | Disconnect guest tlb parameters from TCG compilation. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add page_bits and page_mask to TCGContextRichard Henderson2023-05-161-3/+3
| | | | | | | | | | | | | | | Disconnect guest page size from TCG compilation. While this could be done via exec/target_page.h, we want to cache the value across multiple memory access operations, so we might as well initialize this early. The changes within tcg/ are entirely mechanical: sed -i s/TARGET_PAGE_BITS/s->page_bits/g sed -i s/TARGET_PAGE_MASK/s->page_mask/g Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TLRichard Henderson2023-05-161-5/+3
| | | | | | | | All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode being used. Add a field into TCGLabelQemuLdst to record the usage. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Adjust type of tlb_maskRichard Henderson2023-05-161-2/+2
| | | | | | | | | | | | Because of its use on tgen_arithi, this value must be a signed 32-bit quantity, as that is what may be encoded in the insn. The truncation of the value to unsigned for 32-bit guests is done via the REX bit via 'trexw'. Removes the only uses of target_ulong from this tcg backend. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Conditionalize tcg_out_extu_i32_i64Richard Henderson2023-05-161-1/+3
| | | | | | | | | | Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson2023-05-161-3/+3
| | | | | | | | Keep all 32-bit values zero extended in the register, not solely when addresses are 32 bits. This eliminates a dependency on TARGET_LONG_BITS. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Split INDEX_op_qemu_{ld,st}* for guest address sizeRichard Henderson2023-05-161-33/+52
| | | | | | | | | | | | | For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address. Create the new opcodes and update all users. Since we have not yet eliminated TARGET_LONG_BITS, only one of the two opcodes will ever be used, so we can get away with treating them the same in the backends. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use atom_and_align_for_opcRichard Henderson2023-05-161-12/+15
| | | | | | | | | No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the relevant functions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add INDEX_op_qemu_{ld,st}_i128Richard Henderson2023-05-161-0/+2
| | | | | | | | Add opcodes for backend support for 128-bit memory operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce tcg_target_has_memory_bswapRichard Henderson2023-05-162-3/+5
| | | | | | | | Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro with a function with a memop argument. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use full load/store helpers in user-only modeRichard Henderson2023-05-161-48/+4
| | | | | | | | | Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Add have_atomic16Richard Henderson2023-05-162-0/+28
| | | | | | | | Notice when Intel or AMD have guaranteed that vmovdqa is atomic. The new variable will also be used in generated code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson2023-05-161-28/+2
| | | | | | | | | | | | With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions. Hoist the qemu_{ld,st}_helpers arrays to tcg.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Set P_REXW in tcg_out_addi_ptrRichard Henderson2023-05-161-1/+1
| | | | | | | | | | The REXW bit must be set to produce a 64-bit pointer result; the bit is disabled in 32-bit mode, so we can do this unconditionally. Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1592 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1642 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Convert tcg_out_qemu_st_slow_pathRichard Henderson2023-05-111-53/+4
| | | | | | | | | Use tcg_out_st_helper_args. This eliminates the use of a tail call to the store helper. This may or may not be an improvement, depending on the call/return branch prediction of the host microarchitecture. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Convert tcg_out_qemu_ld_slow_pathRichard Henderson2023-05-111-43/+28
| | | | | | | Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use indexed addressing for softmmu fast pathRichard Henderson2023-05-111-15/+10
| | | | | | | | | | Since tcg_out_{ld,st}_helper_args, the slow path no longer requires the address argument to be set up by the tlb load sequence. Use a plain load for the addend and indexed addressing with the original input address register. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>