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* tcg-mips: Name the opcode enumerationRichard Henderson2014-05-241-9/+9
| | | | | | | And use it in the opcode emission functions. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Use EXT for AND on mips32r2Richard Henderson2014-05-242-14/+50
| | | | | | | At the same time, tidy deposit by introducing tcg_out_opc_bf. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Use T9 for TCG_TMP1Richard Henderson2014-05-241-1/+1
| | | | | | | | | T0 is an argument register for the n32 and n64 abis. T9 is the call address register for the abis, and is more directly under the control of the backend. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Introduce TCG_TMP0, TCG_TMP1Richard Henderson2014-05-241-114/+117
| | | | | | | Use these instead of hard-coding the registers to use for temporaries. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Rearrange register allocationRichard Henderson2014-05-242-11/+19
| | | | | | | | | | | | Use FP (also known as S8) as a normal call-saved register. Include T0 in the allocation order and call-clobbered list even though it's currently used as a TCG temporary. Put the argument registers at the end of the allocation order. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Convert to new_ldstRichard Henderson2014-05-242-53/+25
| | | | | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Convert to new qemu_l/st helpersRichard Henderson2014-05-241-51/+56
| | | | | | | | In addition, fill delay slots calling the helpers and tail call to the store helpers. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Move softmmu slow path out of lineRichard Henderson2014-05-241-389/+383
| | | | | | | | | At the same time, tidy up the call helpers, avoiding a memory reference. Split out several subroutines. Use TCGMemOp constants. Make endianness selectable at runtime. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Split large ldst offsetsRichard Henderson2014-05-241-11/+12
| | | | | | | Use this to reduce goto_tb by one insn. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Fill the exit_tb delay slotRichard Henderson2014-05-241-7/+18
| | | | | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Use J and JAL opcodesRichard Henderson2014-05-241-6/+40
| | | | | | | | For userland builds calls will normally be in range, and for the exit_tb opcode the branch to the epilogue. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson2014-05-121-14/+3
| | | | | | | | | | | The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Split out tcg_out_callRichard Henderson2014-05-121-8/+10
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson2014-05-122-80/+37
| | | | | | | And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Use HOST_WORDS_BIGENDIANRichard Henderson2014-04-182-10/+6
| | | | | | Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Relax requirement for mulu2_i32 on 32-bit hostsRichard Henderson2014-04-181-0/+1
| | | | | | | Instead require either mulu2_i32 or muluh_i32. The code in tcg-op.h already supports looking for both. Previous incomplete conversion? Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson2014-04-181-1/+1
| | | | | | | | Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add qemu_ld_st_i32/64Richard Henderson2013-10-101-0/+2
| | | | | | | Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add tcg-be-null.hRichard Henderson2013-10-101-0/+2
| | | | | | | | | This is a no-op backend data implementation, for those targets that are not currently using the load/store optimization path. This is prepatory to always requiring these functions in all backends. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge branch 'tcg-next' of git://github.com/rth7680/qemuAurelien Jarno2013-09-032-15/+23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'tcg-next' of git://github.com/rth7680/qemu: (29 commits) tcg-i386: Make use of zero-extended memory helper routines tcg: Introduce zero and sign-extended versions of load helpers exec: Split softmmu_defs.h target: Include softmmu_exec.h where forgotten exec: Rename USUFFIX to LSUFFIX tcg-i386: Don't perform GETPC adjustment in TCG code exec: Reorganize the GETRA/GETPC macros configure: Allow x32 as a host tcg-i386: Adjust tcg_out_tlb_load for x32 tcg-i386: Use intptr_t appropriately tcg: Fix jit debug for x32 tcg: Use appropriate types in tcg_reg_alloc_call tcg: Change tcg_out_ld/st offset to intptr_t tcg: Change tcg_gen_exit_tb argument to uintptr_t tcg: Use uintptr_t in TCGHelperInfo tcg: Change relocation offsets to intptr_t tcg: Change memory offsets to intptr_t tcg: Change frame pointer offsets to intptr_t tcg: Define TCG_ptr properly tcg: Define TCG_TYPE_PTR properly ...
| * exec: Split softmmu_defs.hRichard Henderson2013-09-021-3/+0
| | | | | | | | | | | | | | | | | | | | | | The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson2013-09-021-2/+2
| | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Change relocation offsets to intptr_tRichard Henderson2013-09-021-8/+8
| | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson2013-09-021-2/+1
| | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg-mips: Implement mulsh, muluhRichard Henderson2013-09-022-2/+12
| | | | | | | | | | | | | | | | With the optimization in tcg_liveness_analysis, we can avoid the MFLO when it is unused. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Add muluh and mulsh opcodesRichard Henderson2013-09-021-0/+2
| | | | | | | | | | | | | | | | Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg/mips: only enable ext8s/ext16s ops on MIPS32R2Aurelien Jarno2013-09-032-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On MIPS ext8s and ext16s ops are implemented with a dedicated instruction only on MIPS32R2, otherwise the same kind of implementation than at TCG level (shift left followed by shift right) is used. Change that by only implementing the ext8s and ext16s ops on MIPS32R2 so that optimizations can be done by the optimizer. Use an inline version to avoid having to test again for MIPS32R2 instructions. Keep the shift implementation for the ld/st routines. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/mips: inline bswap16/bswap32 opsAurelien Jarno2013-09-031-4/+3
| | | | | | | | | | | | | | | | | | Use an inline version for the bswap16 and bswap32 ops to avoid testing for MIPS32R2 instructions availability, as these ops are only available in that case. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | tcg/mips: detect available host instructions at runtimeAurelien Jarno2013-09-032-92/+171
|/ | | | | | | | | | | | | | Now that TCG supports enabling and disabling ops at runtime, it's possible to detect the available host instructions at runtime, and enable the corresponding ops accordingly. Unfortunately it's not easy to probe for available instructions on MIPS, the information is partially available in /proc/cpuinfo, and not available in AUXV. This patch therefore probes for the instructions by trying to execute them and by catching a possible SIGILL signal. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: fix invalid op definition errorsJames Hogan2013-08-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | tcg/mips/tcg-target.h defines various operations conditionally depending upon the isa revision, however these operations are included in mips_op_defs[] unconditionally resulting in the following runtime errors if CONFIG_DEBUG_TCG is defined: Invalid op definition for movcond_i32 Invalid op definition for rotl_i32 Invalid op definition for rotr_i32 Invalid op definition for deposit_i32 Invalid op definition for bswap16_i32 Invalid op definition for bswap32_i32 tcg/tcg.c:1196: tcg fatal error Fix with ifdefs like the i386 backend does for movcond_i32. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Split rem requirement from div requirementRichard Henderson2013-07-091-0/+1
| | | | | | | | There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/mips: Implement muls2_i32Aurelien Jarno2013-04-012-1/+7
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Add signed multiword multiplication operationsRichard Henderson2013-02-231-0/+1
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* janitor: add guards to headersPaolo Bonzini2012-12-191-0/+3
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg/mips: use MUL instead of MULT on MIPS32 and aboveAurelien Jarno2012-10-301-0/+7
| | | | | | | | | MIPS32 and later instruction sets have a multiplication instruction directly operating on GPRs. It only produces a 32-bit result but it is exactly what is needed by QEMU. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell2012-10-121-3/+0
| | | | | | | | | | GUEST_BASE support is now supported by all TCG backends, and is now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE define (set by every backend) and the error if it is unset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* tcg: remove obsolete jmp opAurelien Jarno2012-10-061-5/+0
| | | | | | | | | | | | | The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: fix MIPS32(R2) detectionAurelien Jarno2012-09-262-9/+9
| | | | | | | | Fix the MIPS32(R2) cpu detection so that it also works with -march=octeon. Thanks to Andrew Pinski for the hint. Cc: Andrew Pinski <apinski@cavium.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "tcg/mips"Aurelien Jarno2012-09-221-2/+2
| | | | | | | | This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad. This commit was not supposed to be pushed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mipsAurelien Jarno2012-09-221-2/+2
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* tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil2012-09-221-6/+0
| | | | | | | | | | | | | The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: implement movcond op on MIPS32R2Aurelien Jarno2012-09-222-0/+77
| | | | | | | | movcond operation can be implemented on MIPS32 Release 2 using the MOVN, MOVZ, SLT and SLTU instructions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: implement deposit op on MIPS32R2Aurelien Jarno2012-09-222-1/+10
| | | | | | | | deposit operations can be optimized on MIPS32 Release 2 using the INS instruction. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: implement rotl/rotr ops on MIPS32R2Aurelien Jarno2012-09-222-1/+22
| | | | | | | | | rotr operations can be optimized on MIPS32 Release 2 using the ROTR and ROTRV instructions. Also implemented rotl operations by subtracting the shift from 32. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: optimize bswap{16,16s,32} on MIPS32R2Aurelien Jarno2012-09-222-7/+38
| | | | | | | | | | | | | | | bswap operations can be optimized on MIPS32 Release 2 using the ROTR, WSBH and SEH instructions. We can't use the non-R2 code to implement the ops due to registers constraints, so don't define the corresponding TCG_TARGET_HAS_bswap* values. Also bswap16* operations are supposed to be called with the 16 high bits zeroed. This is the case everywhere (including for TCG by definition) except when called from the store helper. Remove the AND instructions from bswap16* and move it there. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: optimize brcond arg, 0Aurelien Jarno2012-09-221-8/+30
| | | | | | | | MIPS has some conditional branch instructions when comparing with zero. Use them. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: use stack for TCG tempsAurelien Jarno2012-09-221-4/+6
| | | | | | | | Use stack instead of temp_buf array in CPUState for TCG temps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: don't use global pointerAurelien Jarno2012-09-221-1/+1
| | | | | | | Don't use the global pointer in TCG, in case helpers try access global variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: use TCGArg or TCGReg instead of intAurelien Jarno2012-09-221-28/+35
| | | | | | | | | Instead of int, use the correct TCGArg and TCGReg type: TCGReg when representing a TCG target register, TCGArg when representing the latter or a constant. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>